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参数资料
| 型号： | HY5DU56422ALF-J |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | FBGA-60 |
| 文件页数： | 36/36页 |
| 文件大小： | 395K |
| 代理商： | HY5DU56422ALF-J |
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Rev. 0.1/Apr. 02
9
HY5DU56422A(L)F
HY5DU56822A(L)F
HY5DU561622A(L)F
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
ADDR
A10/
AP
BA
Note
Extended Mode Register Set
H
X
LLLL
OP code
1,2
Mode Register Set
H
X
LLLL
OP code
1,2
Device Deselect
HX
H
XXX
X1
No Operation
L
HHH
Bank Active
H
X
L
H
RA
V
1
Read
H
X
LHLH
CA
L
V
1
Read with Autoprecharge
H1,3
Write
HX
L
H
L
CA
L
V
1
Write with Autoprecharge
H1,4
Precharge All Banks
HX
L
H
L
X
HX
1,5
Precharge selected Bank
LV
1
Read Burst Stop
H
X
L
H
L
X
1
Auto Refresh
H
LLL
H
X
1
Self Refresh
Entry
H
L
LLL
H
X
1
Exit
L
H
XXX
1
L
HHH
Precharge Power
Down Mode
Entry
H
L
H
XXX
X
1
L
HHH
1
Exit
L
H
XXX
1
L
HHH
1
Active Power
Down Mode
Entry
H
L
H
XXX
X
1
L
VVV
1
Exit
L
H
X
1
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5DU56422ALT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mx4|2.5V|8K|J/M/K/H/L|DDR SDRAM - 256M |
| HY5DU56422ALT-H | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-J | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-K | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-L | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
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