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参数资料
| 型号： | HY5DU56422ALF-J |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | FBGA-60 |
| 文件页数： | 18/36页 |
| 文件大小： | 395K |
| 代理商： | HY5DU56422ALF-J |
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Rev. 0.1/Apr. 02
25
HY5DU56422A(L)F
HY5DU56822A(L)F
HY5DU561622A(L)F
DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
32Mx8
Parameter
Symbol
Test Condition
Speed
Unit Note
-J
-M
-K
-H
-L
Operating Current
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
105
95
90
mA
Operating Current
IDD1
One bank; Active - Read - Precharge;
Burst=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
per clock cycle; IOUT=0mA
150
130
120
mA
Precharge Power
Down Standby
Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
20
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs
changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
50
40
35
mA
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode ;
CKE=Low, tCK=tCK(min)
25
mA
Active Standby
Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
60
50
mA
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
290
250
190
mA
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
290
250
190
mA
Auto Refresh Current
IDD5
tRC=tRFC(min); All banks active
230
210
195
mA
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Normal
3mA
Low Power
1.5
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4, Refer to
the following page for detailed test condition
315
305
280
mA
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5DU56422ALT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mx4|2.5V|8K|J/M/K/H/L|DDR SDRAM - 256M |
| HY5DU56422ALT-H | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-J | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-K | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-L | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
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