参数资料
型号: IDT49C465PQF8
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 算术逻辑单元
英文描述: 49C SERIES, 32-BIT ERROR DETECT AND CORRECT CKT, PQFP144
封装: PLASTIC, QFP-144
文件页数: 22/39页
文件大小: 299K
代理商: IDT49C465PQF8
29
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
AC TIMING DIAGRAMS—32-BIT CONFIGURATION
Figure 7. 32-Bit Generate Timing
M DA TA OUT = S DA TAIN
Parameter
Name
P ropagation Delay
From
To
Min./
Max.
BE N - Low to SD OUT D isabled
tB ESxZ m in.
tBE SxZ m ax.
BE N - Low to SD OUT D isabled
SOE - Low to SDOUT D isabled
tS ESxZ m in.
tSE SxZ m ax.
SOE - Low to SDOUT D isabled
SDIN S et-up to SLEIN = Low
tSSLS
tS SLH
SDIN H old to SLEIN = Low
tSP E
SDIN to PER ROUT
tPP E
PX to P ER ROUT
SD IN to M DOUT
tS M
tSLM
SLE = H igh to M D OUT
(1)
tM EM Zx
MOE = Low to M D OUT E nabled
SD IN to C BO
tSC
tS LC
S LE = H igh to CB O
tC ECZx
CBOE = Low to C BO Enable
(1)
min.
max.
min.
max.
min.
max.
CB OE
CB O
BEN
SOE
SD0-31
SLE
PN
PER R
MOE
MD0-31
to
1
2
3
4
5
(OU TPUT)
DA TAIN
to
1
234
5
tB ESxZ
tBE SxZ
tS ESxZ
tSE SxZ
tSS LS
tS SLH
tSP E
tPP E
tS M
tSLM
(1)
tM EM Zx
(INP UT)
tC ECZx
tSLC
(1)
tSC
max.
NOTE:
1. Assumes that System Data is valid at least 3ns (Com.) before SLE goes HIGH.
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