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参数资料
| 型号： | IDT49C465PQF8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 算术逻辑单元 |
| 英文描述： | 49C SERIES, 32-BIT ERROR DETECT AND CORRECT CKT, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 37/39页 |
| 文件大小： | 299K |
| 代理商： | IDT49C465PQF8 |
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7
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
I/O
Name and Function
I/O Buses and Controls
SD0-7
SD8-15
SD16-23
I/O
System Data Bus: Data from the MD0-31 appears at these pins corrected if MODE 2-0 = x11, or uncorrected in the other modes. The
BEn inputs must be HIGH and the SOE pin must be LOW to enable the SD output buffers during a read cycle. (Also, see diagnostic
section.)
SD24-31
Separate I/O Memory Systems: In a write or partial-write cycle, the byte not-to-be-modified is output on SDn to n+7 for rewriting to
memory, if BEn is HIGH and SOE is LOW. The new bytes to be written to memory are input on the SDn pins, for writing checkbits to
memory, if BEn is LOW.
Separate I/O Memory Systems: In a write or partial-write cycle, the byte not-to-be-modified is re-directed to the MS I/O pins, if BEn is
HIGH, for checkbit generation and rewriting to memory by the MS I/O pins. SOE must be HIGH to avoid enabling the outputs drivers to the
system bus in this more. The new bytes to be written are input on the SDn pins for checkbit generation and writing to memory. BEn must
be LOW to direct input data from the System Data bus to the MD I/O pins for checkbit generation and writing to the checkbit memory.
SLE
I
System Latch Enable: SLE is an input used to latch data at the SD inputs. the latch is transparent when SLE is HIGH: the data is
latched when SLE is LOW.
PLE
I
Pipeline Latch Enable: PLE is an input which controls a pipeline latch, which controls data to be output on the SD bus and the MD bus
during byte merges. Use of this latch is optional. The latch is transparent when PLE is LOW: the data is latched when PLE is HIGH.
SOE
I
System Output Enable: When LOW, enables System output drivers and Parity outputs drivers if corresponding Byte Enable inputs are
HIGH.
BE0-3
I
Byte Enables: In systems using separate I/O memory buses, BEn is used to enable the SD and Parity outputs for byte n. The BEn pins
also control the “Byte mux”. When BEn is HIGH, the corrected or uncorrected data from the Memory Data latch is directed to the MD I/O
pins and used for the checkbit generation for byte n. This is used in partial-word-write operations or during correction cycles. When BEn is
LOW, the data from the System Data latch is directed to the MD I/O pins and used for the checkbit generation for byte n.
BE0 controls SD0-7
BE1 controls SD8-15
BE0 controls SD16-23
BE1 controls SD24-31
MD0-31
I/O
Memory Data Bus: These I/O pins accept a 32-bit data word from main memory for error detection and/or correction. They also output
corrected old data or new data to be written to main memory when the EDC unit is used in a bidirectional configuration.
MLE
I
Memory Latch Enable: MLE is used to latch data from the MD inputs and checkbits from the CBI inputs. The latch is transparent when
the MLE is HIGH: data is latched when MLE is LOW. When identified as the upper slice in a 64-bit cascade, the checkbit latch is
bypassed.
MOE
I
Memory Output Enable: MOE enables Memory Data Bus output drivers when LOW.
P0-3
I/O
Parity I/O: The parity I/O pins for Bytes 0 to 3. These pins output the parity of their respective bytes when that byte is being output on the
SD bus. These pins also serve as parity inputs and are used in generating the parity ERRor (PERR) signal under certain conditions (see
Byte Enable definition). The parity is odd or even depending on the state of the Parity SELect pin (PSEL).
PSEL
I
Parity SELect: If the Parity SELect pin is LOW, the parity is even. If the Parity SELect pin is HIGH, the parity is odd.
Inputs
CBI0-7
I
CheckBits-In (00)
CheckBits-In-1 (10)
Partial-Syndrome-In (11)
In a single EDC system or in the lower slice of a cascaded EDC system, these inputs accept the checkbits from the checkbit memory. In
the upper slice in a cascaded EDC system, these inputs accept the “Partial-Syndrome” from the lower slice (Detect/Correct path).
PCBI0-7
I
Partial-CheckBits-In (10)
Partial-CheckBits-In (11)
In a single EDC system, these inputs are unused but should not be allowed to float. In a cascaded EDC system, the “Partial-checkbits”
used by the lower slice are accepted by these inputs (Correction path only). In the upper slice of a cascaded EDC system, “Partial
Checkbits” generated by the lower slice are accepted by these inputs (Generate path).
CODE ID 1,0
I
CODE IDentity: Inputs with identify the slice position/ functional mode of the IDT49C465.
(00) Single 32-bit EDC unit
(01) 64-bit “Checkbit-generate-only” unit
(10) Lower slice of a 64-bit cascade
(11) Upper slice of a 64-bit cascade
相关PDF资料 |
PDF描述 |
|---|---|
| IDT49FCT818AEB | 8-BIT, DSP-PIPELINE REGISTER, CDFP24 |
| IDT49FCT818P | 8-BIT, DSP-PIPELINE REGISTER, PDIP24 |
| IDT49FCT818L | 8-BIT, DSP-PIPELINE REGISTER, CQCC28 |
| IDT49FCT818LB | 8-BIT, DSP-PIPELINE REGISTER, CQCC28 |
| IDT49FCT818PB | 8-BIT, DSP-PIPELINE REGISTER, PDIP24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT49C465PQFB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT |
| IDT49C466 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT |
| IDT49C466A | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT |
| IDT49C466APQF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT |
| IDT49C466GB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Error Detection & Correction (EDAC) |
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