15
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
DEFINITIONS OF TERMS
D0 - D31
= System Data and/or Memory Data Inputs
CBI0 - CBI7
= Checkbit Inputs
PCBI0 - PCBI7
= Partial Checkbit Inputs
FS0 - FS7
= Final Internal Syndrome Bits
FUNCTIONAL EQUATIONS
The equations below describe the terms used in the IDT49C465 to
determine the values of the partial checkbits, checkbits, partial
syndromes, and final internal syndromes.
NOTE: All “
⊕” symbols below represent the “EXCLUSIVE-OR” function
PA = D0
⊕ D1 ⊕ D2 ⊕ D4 ⊕ D6 ⊕ D8 ⊕ D10 ⊕ D12 ⊕ D16 ⊕ D17 ⊕
D18
⊕ D20 ⊕ D22 ⊕ D24 ⊕ D26 ⊕ D28
PB = D0
⊕ D3 ⊕ D4 ⊕ D7 ⊕ D9 ⊕ D10 ⊕ D13 ⊕ D15 ⊕ D16 ⊕ D19 ⊕
D20
⊕ D23 ⊕ D25 ⊕ D26 ⊕ D29 ⊕ D31
PB = D0
⊕ D1 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D16 ⊕ D17 ⊕
D21
⊕ D22 ⊕ D23 ⊕ D27 ⊕ D28 ⊕ D29
PD = D2
⊕ D3 ⊕ D4 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D14 ⊕ D15 ⊕ D18 ⊕ D19 ⊕
D20
⊕ D21 ⊕ D22 ⊕ D23 ⊕ D30 ⊕ D31
PE = D8
⊕ D9 ⊕ D10 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D14 ⊕ D15 ⊕ D24 ⊕ D25
⊕ D26 ⊕ D27 ⊕ D28 ⊕ D29 ⊕ D30 ⊕ D31
PF = D0
⊕ D1 ⊕ D2 ⊕ D3 ⊕ D4 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D24 ⊕ D25 ⊕ D26
⊕ D27 ⊕ D28 ⊕ D29 ⊕ D30 ⊕ D31
PG = D8
⊕ D9 ⊕ D10 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D14 ⊕ D15 ⊕ D16 ⊕ D17
⊕ D18 ⊕ D19 ⊕ D20 ⊕ D21 ⊕ D22 ⊕ D23
PH0 = D0
⊕ D4 ⊕ D6 ⊕ D7 ⊕ D8 ⊕ D9 ⊕ D11 ⊕ D14 ⊕ D17 ⊕ D18 ⊕
D19
⊕ D21 ⊕ D26 ⊕ D28 ⊕ D29 ⊕ D31
PH1 = D1
⊕ D2 ⊕ D3 ⊕ D5 ⊕ D8 ⊕ D9 ⊕ D11 ⊕ D14 ⊕ D17 ⊕ D18 ⊕
D19
⊕ D21 ⊕ D24 ⊕ D25 ⊕ D27 ⊕ D30
PH2 = D0
⊕ D4 ⊕ D6 ⊕ D7 ⊕ D10 ⊕ D12 ⊕ D13 ⊕ D15 ⊕ D16 ⊕ D20 ⊕
D22
⊕ D23 ⊕ D26 ⊕ D28 ⊕ D29 ⊕ D31
CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account when
applying high-speed CMOS products to the automatic test environment.
Large output currents are being switched in very short periods and
proper testing demands that test set-ups have minimized inductance and
guaranteed zero voltage grounds. The techniques listed below will
assist the user in obtaining accurate testing results.
1. All input pins should be connected to a voltage potential during
testing. If left floating, the device may oscillate, causing improper
device operation and possible latchup.
2. Placement and value of decoupling capacitors is critical. Each
physical set-up has different electrical characteristics and it is
recommended that various decoupling capacitor sizes be
experimented with. Capacitors should be positioned using the
minimum lead lengths. They should also be distributed to decouple
power supply lines and be placed as close as possible to the DUT
power pins.
3. Device grounding is extremely critical for proper device testing. The
use of multi-layer performance boards with radial decoupling
between power and ground planes is necessary. The ground plane
must be sustained from the performance board to the DUT interface
board. Wiring unused interconnect pins to the ground plane is
recommended. Heavy gauge stranded wire should be used for
power wiring, with twisted pairs being recommended for minimized
inductance.
4. To guarantee data sheet compliance, the input thresholds should be
tested per input pin in a static environment. To allow for testing and
hardware-induced noise, IDT recommends using the VIL
≤ 0V and
VIH
≥ 3V for AC tests.