参数资料
型号: IDT70P257L55BYGI
厂商: IDT, Integrated Device Technology Inc
文件页数: 18/23页
文件大小: 0K
描述: IC SRAM 128KBIT 55NS 100BGA
标准包装: 90
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 128K(8K x 16)
速度: 55ns
接口: 并联
电源电压: 1.7 V ~ 1.9 V
工作温度: -40°C ~ 85°C
封装/外壳: 100-VFBGA
供应商设备封装: 100-CABGA(6x6)
包装: 托盘
其它名称: 70P257L55BYGI
800-1374
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Truth Table V — Example of Semaphore Procurement Sequence (1,2,3)
Functions
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
D 0 - D 15 Left
1
0
0
1
1
0
1
1
1
0
1
D 0 - D 15 Right
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5684 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70P257/247.
2. There are eight semaphore flags written to via I/O 0 and read from all I/O's (I/O 0 -I/O 15 ). These eight semaphores are addressed by A 0 -A 2 .
3. CE = V IH , SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Truth Table VI — Input Read Register Operation (3)
SFEN
H
L
CE
L
L
R/ W
H
H
OE
L
L
UB
L (1)
X
LB
L (1)
L
ADDR
x0000 - Max
x0000
I/O 0 -I/O 1
VALID (1)
VALID (2)
I/O 2 -I/O 15
VALID (1)
X
Mode
Standard Memory Access
IRR Read (3)
5684 tbl 18
NOTES:
1. UB or LB = V IL . If LB = V IL , then I/O 0 - I/O 7 are VALID. If UB = V IL , then I/O 8 - I/O 15 are VALID.
2. LB must be active ( LB = V IL ) for these bits to be valid.
3. SFEN = V IL to activate IRR reads.
Truth Table VII — Output Drive Register Operation (5)
X
L
L
VALID
VALID
VALID
SFEN
H
L
L
CE
L
L
L
R/ W
H
L
H
OE
(1)
X
L
UB
(2)
X
X
LB
(2)
L
L
ADDR
x0000 - Max
x0001
x0001
I/O 0 -I/O 4
(2)
VALID (3)
(3)
I/O 5 -I/O 15
(2)
X
X
Mode
Standard Memory Access
ODR Write (4,5)
ODR Read (5)
5684 tbl 19
NOTES:
1. Output enable must be low (OE = Vil) during reads for valid data to be output.
2. UB or LB = V IL . If LB = V IL , then I/O 0 - I/O 7 are VALID. If UB = V IL , then I/O 8 - I/O 15 are VALID.
3. LB must be active ( LB = V IL ) for these bits to be valid.
4. During ODR writes data will also be written to the memory.
5. SFEN = V IL to activate ODR reads and writes.
18
6.42
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