参数资料
型号: IDT70T631S
厂商: Integrated Device Technology, Inc.
英文描述: 122 x 32 pixel format, Compact LCD size
中文描述: 高速2.5V的512/256K与3.3V 5011 2.5V的接口× 18 ASYNCHRONO美国双端口静态RAM
文件页数: 20/27页
文件大小: 342K
代理商: IDT70T631S
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing
(1)
t
WC
Preliminary
20
Truth Table III — Interrupt Flag
(1,4)
Left Port
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3.
CE
X
= V
IL
means
CE
0
X
= V
IL
and CE
1
X
= V
IH
.
CE
X
= V
IH
means
CE
0
X
= V
IH
and/or CE
1
X
= V
IL
.
4. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
5. Timing depends on which enable signal (
CE
or R/
W
) is de-asserted first.
NOTES:
1. Assumes
BUSY
L
=
BUSY
R
=V
IH
.
CE
X
= L means
CE
0
X
= V
IL
and CE
1
X
= V
IH
.
2. If
BUSY
L
= V
IL
, then no change.
3. If
BUSY
R
= V
IL
, then no change.
4.
INT
L
and
INT
R
must be initialized at power-up.
5. A
18x
is a NC for IDT70T631. Therefore, Interrupt Addresses are 3FFFF and 3FFFE.
5670 drw 18
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"(3)
R/
W
"A"
t
AS
t
WR
(4)
(5)
t
INS
(4)
INT
"B"
(2)
.
5670 drw 19
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"(3)
OE
"B"
t
AS
t
RC
(4)
t
INR
(4)
INT
"B"
(2)
.
Right Port
Function
R/
W
L
CE
L
OE
L
A
18L
-A
0L
(5)
INT
L
R/
W
R
CE
R
OE
R
A
18R
-A
0R
(5)
INT
R
L
L
X
7FFFF
X
X
X
X
X
L
(2)
Set Right
INT
R
Flag
X
X
X
X
X
X
L
L
7FFFF
H
(3)
Reset Right
INT
R
Flag
X
X
X
X
L
(3)
L
L
X
7FFFE
X
Set Left
INT
L
Flag
X
L
L
7FFFE
H
(2)
X
X
X
X
X
Reset Left
INT
L
Flag
5670 tbl 17
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