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参数资料
| 型号： | IDT72V36110L6BBG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/48页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 131KX36 6NS 144BGA |
| 标准包装： | 1 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.7M（131K x 36） |
| 数据速率： | 166MHz |
| 访问时间： | 4ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA |
| 供应商设备封装： | 144-PBGA（13x13） |
| 包装： | 托盘 |
| 其它名称： | 72V36110L6BBG |
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18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programmingof
PAEandPAFvaluescanbeachievedbyusingacombination
ofthe
LD,SEN,WCLKandSIinputpins.ProgrammingPAEandPAFproceeds
as follows: when
LD and SEN are set LOW, data on the SI input are written,
onebitforeachWCLKrisingedge,startingwiththeEmptyOffsetLSBandending
with the Full Offset MSB. A total of 32 bits for the IDT72V36100 and 34 bits for
the IDT72V36110. See Figure 15, Serial Loading of Programmable Flag
Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively.
PAEandPAFcanshowavalidstatusonlyafterthecompleteset
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does
not have to occur at once. A select number of bits can be written to the SI input
and then, by bringing
LDandSENHIGH,datacanbewrittentoFIFOmemory
via Dn by toggling
WEN. When WEN is brought HIGH with LD and SEN
restored to a LOW, the next offset bit in sequence is written to the registers via
SI. Ifaninterruptionofserialprogrammingisdesired,itissufficienteithertoset
LDLOWanddeactivateSENortosetSENLOWanddeactivateLD. OnceLD
and
SENarebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. MeasuringfromtherisingWCLKedgethatachievestheabovecriteria;
PAFwillbevalidaftertwomorerisingWCLKedgesplustPAF,PAEwillbevalid
after the next two rising RCLK edges plus tPAE plus tSKEW2.
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn.
PARALLEL MODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programmingof
PAEandPAFvaluescanbeachievedbyusingacombination
of the
LD, WCLK , WEN and Dn input pins. Programming PAE and PAF
proceedsasfollows:
LDandWENmustbesetLOW.Forx36bitinputbuswidth,
dataontheinputsDnarewrittenintotheEmptyOffsetRegisteronthefirstLOW-
to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of
WCLK,dataarewrittenintotheFullOffsetRegister.ThethirdtransitionofWCLK
writes, once again, to the Empty Offset Register. For x18 bit input bus width,
dataontheinputsDnarewrittenintotheEmptyOffsetRegisterLSBonthefirst
LOW-to-HIGH transition of WCLK. Upon the 2nd LOW-to-HIGH transition of
WCLKdataarewrittenintotheEmptyOffsetRegisterMSB.Thethirdtransition
ofWCLKwritestotheFullOffsetRegisterLSB,thefourthtransitionofWCLKthen
writes to the Full Offset Register MSB. The fifth transition of WCLK writes once
againtotheEmptyOffsetRegisterLSB. Atotaloffourwritestotheoffsetregisters
is required to load values using a x18 input bus width. For an input bus width
ofx9bits,atotalofsixwritecyclestotheoffsetregistersisrequiredtoloadvalues.
See Figure 3, Programmable Flag Offset Programming Sequence. See
Figure 16, Parallel Loading of Programmable Flag Registers, for the timing
diagram for this mode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing
LD HIGH, write operations can be redirected to
theFIFOmemory.When
LDissetLOWagain,andWENisLOW,thenextoffset
register in sequence is written to. As an alternative to holding
WEN LOW and
toggling
LD,parallelprogrammingcanalsobeinterruptedbysetting LDLOW
and toggling
WEN.
Note that the status of a programmable flag (
PAEorPAF)outputisinvalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria;
PAF will be valid after
twomorerisingWCLKedgesplustPAF,
PAEwillbevalidafterthenexttworising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Qn
pins when
LDissetLOWandRENissetLOW.Forx36outputbuswidth,data
are read via Qn from the Empty Offset Register on the first LOW-to-HIGH
transitionofRCLK.UponthesecondLOW-to-HIGHtransitionofRCLK,dataare
read from the Full Offset Register. The third transition of RCLK reads, once
again, from the Empty Offset Register. For x18 output bus width, a total of four
readcyclesarerequiredtoobtainthevaluesoftheoffsetregisters.Startingwith
the Empty Offset Register LSB and finishing with the Full Offset Register MSB.
Forx9outputbuswidth,atotalofsixreadcyclesmustbeperformedontheoffset
registers. See Figure 3, Programmable Flag Offset Programming Sequence.
See Figure 17, Parallel Read of Programmable Flag Registers, for the timing
diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting
REN,LD,
or both together. When
REN and LD are restored to a LOW level, reading of
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of memory.
Retransmitsetupisinitiatedbyholding
RTLOWduringarisingRCLKedge.
REN andWEN must be HIGH before bringingRT LOW. Whenzerolatencyis
utilized,
RENdoesnotneedtobeHIGHbeforebringingRTLOW. Atleasttwowords,
butnomorethanD-2 words should have been written into the FIFO, and read
from the FIFO, between Reset (Master or Partial) and the time of Retransmit
setup. D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmitsetupbysetting
EFLOW. Thechangeinlevelwillonlybenoticeable
if
EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When
EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on
REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V36110L6BBG8 | 功能描述:IC FIFO SYNC 131KX36 6NS 144BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V36110L6PF | 功能描述:IC FIFO SYNC 131KX36 6NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V36110L6PF8 | 功能描述:IC FIFO SYNC 131KX36 6NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V36110L6PFG | 功能描述:IC FIFO SYNC 131KX36 6NS 128QFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:74ABT 功能:同步，双端口 存储容量:4.6K（64 x 36 x2） 数据速率:67MHz 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:120-LQFP 裸露焊盘 供应商设备封装:120-HLQFP（14x14） 包装:托盘 产品目录页面:1005 (CN2011-ZH PDF) 其它名称:296-3984 |
| IDT72V36110L7-5BB | 功能描述:IC FIFO 131KX36 7-5NS 144BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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