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参数资料
| 型号： | IDT72V36110L6BBG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 15/48页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 131KX36 6NS 144BGA |
| 标准包装： | 1 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.7M（131K x 36） |
| 数据速率： | 166MHz |
| 访问时间： | 4ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA |
| 供应商设备封装： | 144-PBGA（13x13） |
| 包装： | 托盘 |
| 其它名称： | 72V36110L6BBG |
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22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
BUS-MATCHING (BM, IW, OW)
ThepinsBM,IWandOWareusedtodefinetheinputandoutputbuswidths.
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 4 for Bus-
Matching Byte Arrangement.
BIG-ENDIAN/LITTLE-ENDIAN (
BE )
During Master Reset, a LOW on
BE will select Big-Endian operation. A
HIGH on
BEduringMasterResetwillselectLittle-Endianformat.Thisfunction
is useful when the following input to output bus widths are implemented: x36 to
x18, x36 to x9, x18 to x36 and x9 to x36. If Big-Endian mode is selected, then
themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead
outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (
BE) pin. See
Figure 4 for Bus-Matching Byte Arrangement.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Program-
mableflagtimingmode.AHIGHonPFMwillselectSynchronousProgrammable
flag timing mode. If asynchronous
PAF/PAE configuration is selected (PFM,
LOW during
MRS),thePAEisassertedLOWontheLOW-to-HIGHtransition
of RCLK.
PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
Similarly,the
PAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous
PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the
PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly,
PAFisassertedandupdatedontherisingedgeofWCLK
only and not RCLK. The mode desired is configured during master reset by the
state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.
A HIGHwillselectInterspersedParitymode.TheIPbitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bits are located in bit position D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D28 are is assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin. Interspersed Parity control only has an
effectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthedata
written to and read from the FIFO.
OUTPUTS:
FULL FLAG (
FF/IR )
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (
FF) function
is selected. When the FIFO is full,
FF will go LOW, inhibiting further write
operations. When
FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either
MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110). See
Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the
relevanttiminginformation.
In FWFT mode, the Input Ready (
IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
anyfreespaceleft,
IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads
are performed after a reset (either
MRSorPRS),IRwillgoHIGHafterD writes
totheFIFO(D = 65,537fortheIDT72V36100and131,073fortheIDT72V36110).
See Figure 9, Write Timing (FWFT Mode), for the relevant timing information.
The
IRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert
IRisonegreaterthanneededto
assert
FF in IDT Standard mode.
FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare
double register-buffered outputs.
EMPTY FLAG (
EF/OR )
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (
EF)
functionisselected. WhentheFIFOisempty,
EFwillgoLOW,inhibitingfurther
read operations. When
EFisHIGH,theFIFOisnotempty.SeeFigure8,Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
therelevanttiminginformation.
InFWFTmode,theOutputReady(
OR)functionisselected.ORgoesLOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs.
ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
the last word from the FIFO memory to the outputs.
OR goes HIGH only with
a true read (RCLK with
REN = LOW). The previous data stays at the outputs,
indicatingthelastwordwasread. Furtherdatareadsareinhibiteduntil
ORgoes
LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF is a double register-buffered output. In FWFT
mode,
OR isatripleregister-bufferedoutput.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF )
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS),PAFwillgoLOWafter(D - m)wordsarewritten
totheFIFO. The
PAFwillgoLOWafter(65,536-m)writesfortheIDT72V36100
and (131,072-m) writes for the IDT72V36110. The offset “m” is the full offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAF will go LOW after (65,537-m) writes for the
IDT72V36100 and (131,073-m) writes for the IDT72V36110, where m is the
full offset value. The default setting for this value is stated in Table 2.
See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
If asynchronous
PAF configurationisselected,the PAF isassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).
PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). Ifsynchronous
PAF
configuration is selected, the
PAFisupdatedontherisingedgeofWCLK. See
Figure 20, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT
Mode).
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE )
The Programmable Almost-Empty flag (
PAE)willgoLOWwhentheFIFO
reaches the almost-empty condition. In IDT Standard mode,
PAEwillgoLOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 19, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing information.
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相关代理商/技术参数 |
参数描述 |
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| IDT72V36110L6BBG8 | 功能描述:IC FIFO SYNC 131KX36 6NS 144BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V36110L6PF | 功能描述:IC FIFO SYNC 131KX36 6NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V36110L6PF8 | 功能描述:IC FIFO SYNC 131KX36 6NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V36110L6PFG | 功能描述:IC FIFO SYNC 131KX36 6NS 128QFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:74ABT 功能:同步，双端口 存储容量:4.6K（64 x 36 x2） 数据速率:67MHz 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:120-LQFP 裸露焊盘 供应商设备封装:120-HLQFP（14x14） 包装:托盘 产品目录页面:1005 (CN2011-ZH PDF) 其它名称:296-3984 |
| IDT72V36110L7-5BB | 功能描述:IC FIFO 131KX36 7-5NS 144BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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