- 您现在的位置：买卖IC网 > PDF目录9894 > IDT72V36110L6BBG (IDT, Integrated Device Technology Inc)IC FIFO SYNC 131KX36 6NS 144BGA PDF资料下载
参数资料
| 型号： | IDT72V36110L6BBG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 45/48页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 131KX36 6NS 144BGA |
| 标准包装： | 1 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.7M（131K x 36） |
| 数据速率： | 166MHz |
| 访问时间： | 4ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA |
| 供应商设备封装： | 144-PBGA（13x13） |
| 包装： | 托盘 |
| 其它名称： | 72V36110L6BBG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页当前第45页第46页第47页第48页
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
PIN DESCRIPTION (TQFP AND PBGA PACKAGES)
Symbol
Name
I/O
Description
BM(1)
Bus-Matching
I
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size configuration.
BE(1)
Big-Endian/
I
During Master Reset, a LOW on
BE will select Big-Endian operation. A HIGH on BE during Master Reset will
Little-Endian
selectLittle-Endianformat.
D0–D35
DataInputs
I
Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care state.
EF/OR
Empty Flag/
O
In the IDT Standard mode, the
EF function is selected. EF indicates whether or not the FIFO memory is empty.
Output Ready
In FWFT mode, the
OR functionisselected.OR indicateswhetherornotthereisvaliddataavailableattheoutputs.
FF/IR
Full Flag/
O
In the IDT Standard mode, the
FF function is selected. FF indicates whether or not the FIFO memory is full. In the
Input Ready
FWFT mode, the
IR function is selected. IR indicates whether or not there is space available for writing to the FIFO
memory.
FSEL0(1)
Flag Select Bit 0
I
DuringMasterReset,thisinputalongwithFSEL1andthe
LDpin,willselectthedefaultoffsetvaluesfortheprogrammable
flags
PAE and PAF. There are up to eight possible settings available.
FSEL1(1)
Flag Select Bit 1
I
DuringMasterReset,thisinputalongwithFSEL0andthe
LDpinwillselectthedefaultoffsetvaluesfortheprogrammable
flags
PAE and PAF. There are up to eight possible settings available.
FWFT/SI
First Word Fall
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions
Through/Serial In
as a serial input for loading offset registers.
HF
Half-Full Flag
O
HF indicates whether the FIFO memory is more or less than half-full.
IP(1)
Interspersed Parity
I
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity
mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not
effect the data written to and read from the FIFO.
IW(1)
InputWidth
I
This pin, along with OW and MB, selects the bus width of the write port. See Table 1 for bus size configuration.
LD
Load
I
This is a dual purpose pin. During Master Reset, the state of the
LD inputalongwithFSEL0andFSEL1,determines
oneofeightdefaultoffsetvaluesforthe
PAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisterscan
be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the
offsetregisters.
OE
OutputEnable
I
OE controls the output impedance of Qn.
OW(1)
OutputWidth
I
This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
MRS
Master Reset
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset,
theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,oneofeightprogrammable
flagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatency
timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
PAE
Programmable
O
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
Almost-EmptyFlag
register.
PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF
Programmable
O
PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Almost-FullFlag
Full Offset register.
PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
PFM(1)
Programmable
I
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
Flag Mode
will select Synchronous Programmable flag timing mode.
PRS
PartialReset
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all
retained.
Q0–Q35
DataOutputs
O
Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a don’t care
state. Outputs are not 5V tolerant regardless of the state of
OE.
RCLK/
Read Clock/
I
If Synchronous operation of the read port has been selected, when enabled by
REN, the rising edge of RCLK
RD
Read Strobe
reads data from the FIFO memory and offsets from the programmable registers. If
LD is LOW, the values loaded
into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner.
REN should be tied LOW.
Asynchronous operation of the RCLK/RD input is only available in the PBGA package.
REN
Read Enable
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
RM(1)
RetransmitTiming
I
During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
Mode
normal latency mode.
RT
Retransmit
I
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable
flag settings.
RT is useful to reread data from the first physical location of the FIFO.
NOTE:
1. Inputs should not change state after Master Reset.
相关PDF资料 |
PDF描述 |
|---|---|
| MAX1229BCEP+ | IC ADC 12-BIT 300KSPS 20-QSOP |
| MS27472T24B61SB | CONN RCPT 61POS WALL MT W/SCKT |
| MAX1249AEEE+ | IC ADC 10BIT SERIAL 16-QSOP |
| MAX1174BCUP+ | IC ADC 14BIT 135KSPS 20-TSSOP |
| MAX1065BCUI+ | IC ADC 14BIT 165KSPS 28TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V36110L6BBG8 | 功能描述:IC FIFO SYNC 131KX36 6NS 144BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V36110L6PF | 功能描述:IC FIFO SYNC 131KX36 6NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V36110L6PF8 | 功能描述:IC FIFO SYNC 131KX36 6NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V36110L6PFG | 功能描述:IC FIFO SYNC 131KX36 6NS 128QFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:74ABT 功能:同步，双端口 存储容量:4.6K（64 x 36 x2） 数据速率:67MHz 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:120-LQFP 裸露焊盘 供应商设备封装:120-HLQFP（14x14） 包装:托盘 产品目录页面:1005 (CN2011-ZH PDF) 其它名称:296-3984 |
| IDT72V36110L7-5BB | 功能描述:IC FIFO 131KX36 7-5NS 144BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
发布紧急采购，3分钟左右您将得到回复。