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参数资料
| 型号： | IDT72V51246L6BB8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/56页 |
| 文件大小： | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 标准包装： | 1,000 |
| 类型： | 多队列流量控制 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-BGA（17x17） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V51246L6BB8 |
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19
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
READQUEUESELECTIONANDREADOPERATION(STANDARDMODE)
The IDT72V51236/72V51346/72V51256 multi-queue flow-control de-
vices can be configured up to a maximum of 4 queues which data can be read
via a common read port using the data outputs (Qout), read clock (RCLK) and
read enable (
REN).Anoutputenable,OE controlpinisalsoprovidedtoallow
High-Impedance selection of the Qout data outputs. The multi-queue device
read port operates in a mode similar to “First Word Fall Through” on a
SuperSync IDT FIFO, but with the added feature of data output pipelining (see
Figure 10, Write Operations & First Word Fall Through). The queue to be
read is selected by the address presented on the read address bus (RDADD)
during a rising edge on RCLK while read address enable (RADEN) is HIGH.
The state of
REN does not impact the queue selection. The queue selection
is requires 2 RCLK cycles. All subsequent data reads will be from this queue
until another queue is selected.
Standard mode operation is defined as individual words will be read from
the device as opposed to Packet Mode where complete packets may be read.
The read port is designed such that 100% bus utilization can be obtained. This
means that data can be read out of the device on every RCLK rising edge
including the cycle that a new queue is being addressed.
Changing queues requires a minimum of two RCLK cycles on the read port
(see Figure 12, Read Queue Select, Read Operation). RADEN goes high
signaling a change of queue (clock cycle “D”). The address on RDADD at that
time determines the next queue. Data presented during that cycle (“D”) will be
read at “D” (+ t
A), can be read from the active (old) queue (QP), provided REN
isactiveLOW.If
RENisHIGH(inactive)forthisclockcycle,datawillnotberead
from the previous queue. The next cycle’s rising edge (“E”), the read port
discrete empty flag will update to show the empty status of the newly selected
queue (Q
F). The internal pipeline is also loaded at this time (“D”) with the last
word from the previous (old) queue (Q
P) as well as the next word from the new
queue (Q
F). Both of these words will fall through to the output register( provided
the
OE is asserted) consecutively (cycles “E” and “F” respectively) following
the selection of the new queue regardless of the state of
REN,unlessthenew
queue (Q
F) is empty. If the newly selected queue is empty, any reads from that
queue will be prevented. Data cannot be read from an empty queue. The last
word in the data output register (from the previous queue), will remain on the
data bus, but the output valid flag,
OV will go HIGH, to indicate that the data
present is no longer valid. This pipelining effect provides the user with 100%
bus utilization, and brings about the possibility that a “NULL” queue may be
required within a multi-queue device. Null queue operation is discussed in the
next section. Remember that
OE allows the user to place the data output bus
(Qout) into High-Impedance and the data can be read in to the output register
regardless of
OE.
Refer to Table 2, for Read Address Bus arrangement. Also, refer to Figures
12, 14, and 15 for read queue selection and read port operation timing
diagrams.
PACKET MODE OPERATION (PKT = HIGH on Master Reset)
The Packet mode operation provides the capability where, user defined
packets or frames can be written to the device as opposed to Standard mode
where individual words are written. For clarification, in Packet Mode, a packet
can be written to the device with the starting location designated as Transmit
Start of Packet (TSOP) and the ending location designated as Transmit End
of Packet (TEOP). In conjunction, a packet read from the device will be
designated as Receive Start of Packet (RSOP) and a Receive End of Packet
Operation RCLK
RADEN
ESTR
RDADD[5:0]
Read Queue
Select
10
01
Device Select
(Compared to
ID0,1,2)
Read Queue Address
(2 bits = 4 Queues)
543
2
1 0
543
2
1 0
Device Select
(Compared to
ID0,1,2)
X
Flag Bus Device
Selection
5937 drw06
Null-Q
Select Pin
XX
TABLE 2 — READ ADDRESS BUS, RDADD[5:0]
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相关代理商/技术参数 |
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| IDT72V51246L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51246L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51246L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51253L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51253L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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