参数资料
型号: IDT72V51246L6BB8
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/56页
文件大小: 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
标准包装: 1,000
类型: 多队列流量控制
安装类型: 表面贴装
封装/外壳: 256-BBGA
供应商设备封装: 256-BGA(17x17)
包装: 带卷 (TR)
其它名称: 72V51246L6BB8
2
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
DESCRIPTION:
The IDT72V51236/72V51246/72V51256 multi-queue flow-control de-
vices are single chip within which anywhere between 1 and 4 discrete FIFO
queues can be setup. All queues within the device have a common data input
bus, (write port) and a common data output bus, (read port). Data written into
the write port is directed to a respective queue via an internal de-multiplex
operation, addressed by the user. Data read from the read port is accessed
from a respective queue via an internal multiplex operation, addressed by
the user. Data writes and reads can be performed at high speeds up to
166MHz,withaccesstimesof3.7ns.Datawriteandreadoperationsaretotally
independent of each other, a queue maybe selected on the write port and
a different queue on the read port or both ports may select the same queue
simultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
AlmostFullandProgrammableAlmostEmptyflagforeachqueueisprovided.
Two 4 bit programmable flag busses are available, providing status of all
queues, including queues not selected for write or read operations, these flag
busses provide an individual flag per queue.
Bus Matching is available on this device, either port can be 9 bits, 18 bits
or 36 bits wide provided that at least one port is 36 bits wide. When Bus
Matching is used the device ensures the logical transfer of data throughput
in a Little Endian manner.
A packet mode of operation is also provided when the device is configured
for 36 bit input and 36 bit output port sizes. The Packet mode provides the user
with a flag output indicating when at least one (or more) packets of data within a
queueisavailableforreading.ThePacketReadyprovidestheuserwithameans
by which to mark the start and end of packets of data being passed through the
queues. The multi-queue device then provides the user with an internally
generated packet ready status per queue.
The user has full flexibility configuring queues within the device, being able
to program the total number of queues between 1 and 4, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
BothMasterResetandPartialResetpinsareprovidedonthisdevice.AMaster
Reset latches in all configuration setup pins and must be performed before
programmingofthedevicecantakeplace.APartialResetwillresetthereadand
writepointersofanindividualqueue,providedthatthequeueisselectedonboth
the write port and read port at the time of partial reset.
A JTAG test port is provided, here the multi-queue flow-control device has a
fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
See Figure 1,Multi-Queue Flow-Control Device Block Diagramfor an outline
of the functional blocks within the device.
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