参数资料
型号: IDT82P20416DBFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 38/121页
文件大小: 0K
描述: IC LIU T1/E1/J1 16CH SH 484BGA
标准包装: 84
功能: 线路接口单元(LIU)
接口: E1,J1,T1
电路数: 16
电源电压: 1.8V, 3.3V
功率(瓦特): 3.10W
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 484-LFBGA
供应商设备封装: 484-CABGA(19x19)
包装: 托盘
包括: AIS 警报检测器和发生器,回送功能,PRBS 发生器 / 检测器,远程检测器和发生器
IDT82P20416
16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description
23
December 17, 2009
3.2.3
SLICER
The Slicer is used to generate a standard amplitude mark or a space
according to the amplitude of the input signals. The input signal is sliced
at 50% of the peak value.
3.2.4
RX CLOCK & DATA RECOVERY
The Rx Clock & Data Recovery is used to recover the clock signal
from the received data. It is accomplished by an integrated Digital Phase
Locked Loop (DPLL). The recovered clock tracks the jitter in the data
output from the Slicer and keeps the phase relationship between data
and clock during the absence of the incoming pulse.
3.2.5
DECODER
The Decoder is used only when the receive system interface is in
Single Rail NRZ Format mode. When the receive system interface is in
other modes, the Decoder is bypassed automatically. (Refer to
Section 3.2.6 Receive System Interface for the description of the receive
system interface).
In T1/J1 mode, the received signal is decoded by AMI or B8ZS line
code rule. In E1 mode, the received signal is decoded by AMI or HDB3
line code rule. The line code rule is selected by the R_CODE bit (b2,
3.2.6
RECEIVE SYSTEM INTERFACE
The received data can be output to the system side in four modes:
Single Rail NRZ Format mode, Dual Rail NRZ Format mode, Dual Rail
RZ Format mode and Dual Rail Sliced mode, as selected by the
R_MD[1:0] bits (b1~0, RCF1).
If data is output on RDn in NRZ format and the recovered clock is
output on RCLKn, the receive system interface is in Single Rail NRZ
Format mode. In this mode, the data is decoded and updated on the
active edge of RCLKn. RCLKn outputs a 1.544 MHz (in T1/J1 mode) or
2.048 MHz (in E1 mode) clock.
If data is output on RDPn and RDNn in NRZ format and the recov-
ered clock is output on RCLKn, the receive system interface is in Dual
Rail NRZ Format mode. In this mode, the data is un-decoded and
updated on the active edge of RCLKn. RCLKn outputs a 1.544 MHz (in
T1/J1 mode) or 2.048 MHz (in E1 mode) clock.
If data is output on RDPn and RDNn in RZ format and the recovered
clock is output on RCLKn, the receive system interface is in Dual Rail
RZ Format mode. In this mode, the data is un-decoded and updated on
the active edge of RCLKn. RCLKn outputs a 1.544 MHz (in T1/J1 mode)
or 2.048 MHz (in E1 mode) clock.
If data is output on RDPn and RDNn in RZ format directly after
passing through the Slicer, the receive system interface is in Dual Rail
Sliced mode. In this mode, the data is raw sliced and un-decoded.
Table-3 summarizes the multiplex pin used in different receive
system interface.
Table-3 Multiplex Pin Used in Receive System Interface
Receive System
Interface
Multiplex Pin Used On Receive System
Interface
RDn / RDPn
RDNn
RCLKn
Single Rail NRZ Format
RDn 1
RCLKn 2
Dual Rail NRZ Format
RDPn 1
RDNn 1
RCLKn 2
Dual Rail RZ Format
RDPn 1
RDNn 1
RCLKn 2
Dual Rail Sliced
RDPn 1
RDNn 1
Note:
1. The active level on RDn, RDPn and RDNn is selected by the RD_INV bit (b3,
2. The active edge of RCLKn is selected by the RCK_ES bit (b4, RCF1,...).
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