- 您现在的位置：买卖IC网 > PDF目录1924 > IDT82P20416DBFG (IDT, Integrated Device Technology Inc)IC LIU T1/E1/J1 16CH SH 484BGA PDF资料下载
参数资料
| 型号： | IDT82P20416DBFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 53/121页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 16CH SH 484BGA |
| 标准包装： | 84 |
| 功能： | 线路接口单元（LIU） |
| 接口： | E1，J1，T1 |
| 电路数： | 16 |
| 电源电压： | 1.8V, 3.3V |
| 功率（瓦特）： | 3.10W |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 484-LFBGA |
| 供应商设备封装： | 484-CABGA（19x19） |
| 包装： | 托盘 |
| 包括： | AIS 警报检测器和发生器，回送功能，PRBS 发生器 / 检测器，远程检测器和发生器 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页当前第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页
IDT82P20416
16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description
37
December 17, 2009
3.5.4
ALARM INDICATION SIGNAL (AIS) DETECTION AND GEN-
ERATION
3.5.4.1 Alarm Indication Signal (AIS) Detection
AIS is monitored in both the receive path and the transmit path.
When the mark density in the received data or in the data input from
the transmit system side meets certain criteria, AIS is declared or
cleared. In T1/J1 mode, the criteria are in compliance with ANSI T1.231.
In E1 mode, the criteria are in compliance with ITU G.775 or ETSI
details.
When AIS is detected in the receive path, the LAIS_S bit (b6,
STAT1,...) will be set. A transition from ‘0’ to ‘1’ on the LAIS_S bit (b6,
STAT1,...) or any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LAIS_S
bit (b6, STAT1,...) will set the LAIS_IS bit (b6, INTS1,...) to ‘1’, as
selected by the AIS_IES bit (b6, INTES,...). When the LAIS_IS bit (b6,
INTS1,...) is ‘1’, an interrupt will be reported by INT if not masked by the
LAIS_IM bit (b6, INTM1,...).
When AIS is detected in the transmit path, the SAIS_S bit (b7,
STAT1,...) will be set. A transition from ‘0’ to ‘1’ on the SAIS_S bit (b7,
STAT1,...) or any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the
SAIS_S bit (b7, STAT1,...) will set the SAIS_IS bit (b7, INTS1,...) to ‘1’,
as selected by the AIS_IES bit (b6, INTES,...). When the SAIS_IS bit
(b7, INTS1,...) is ‘1’, an interrupt will be reported by INT if not masked by
the SAIS_IM bit (b7, INTM1,...).
AIS may be counted by an internal Error Counte. Refer to
3.5.4.2 (Alarm Indication Signal) AIS Generation
AIS can be generated automatically in the receive path and the
transmit path.
In the receive path, when the ASAIS_LLOS bit (b2, AISG,...) is set,
AIS will be generated automatically once LLOS is detected. When the
ASAIS_SLOS bit (b3, AISG,...) is set, AIS will be generated automati-
cally once SLOS is detected. When AIS is generated, RDPn/RDNn
output all ‘1’s. RCLKn (if available) outputs XCLK.
In the transmit path, when the ALAIS_LLOS bit (b0, AISG,...) is set,
AIS will be generated automatically once LLOS is detected. When the
ALAIS_SLOS bit (b1, AISG,...) is set, AIS will be generated automati-
cally once SLOS is detected. When AIS is generated, TTIPn/TRINGn
output all ‘1’s.
In the transmit path, the AIS transmission is controled by the TXAIS
bit (b4, AISG,...). When the TXAIS bit (b4, AISG,...) is set to ‘1’, all ‘1’s
pattern is transmitted at TTIPn/TRINGn.
AIS generation uses XCLK1 as reference clock.
If pattern (including PRBS, ARB and IB) is generated in the same
direction, the priority of pattern generation is higher. The generated
pattern will overwrite automatic AIS. Refer to Section 3.5.5.1 Pattern
Generation for the output data and clock.
Table-20 AIS Criteria
ITU G.775 for E1 (LAC = 0)
ETSI 300233 for E1 (LAC = 1)
ANSI T1.231 for T1 (LAC = 0 or 1)
AIS Declaring
Less than 3 zeros are received in each of two
consecutive 512-bit data streams.
Less than 3 zeros are received
in a 512-bit data stream.
Less than 9 zeros are received in a 8192-bit stream, i.e., less
than 99.9% of marks in a period of 5.3 ms are received.
AIS Clearing
3 or more zeros are received in each of two
consecutive 512-bit data streams.
3 or more zeros are received in
a 512-bit data stream.
9 or more zeros are received in a 8192-bit data stream.
1. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz
in E1 mode.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT82P20516DBFG | IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P2281PF | TXRX T1/E1/J1 LONG/SHORT 80-TQFP |
| IDT82P2282PF | TXRX T1/J1/E1 2CHAN 100-TQFP |
| IDT82P2284BB | TXRX T1/J1/E1 4CHAN 208-PBGA |
| IDT82P2288BBG | TXRX OCTAL T1/E1/J1 256-PBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82P20416DBFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P20416DBFGBLANK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:16-Channel Short Haul T1/E1/J1 Line Interface Unit |
| IDT82P20516 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:16-Channel Short Haul E1 Line Interface Unit |
| IDT82P20516BFBLANK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:16-Channel Short Haul E1 Line Interface Unit |
| IDT82P20516BFGBLANK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:16-Channel Short Haul E1 Line Interface Unit |
发布紧急采购，3分钟左右您将得到回复。