参数资料
型号: IDT82V3255DK
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 通信及网络
英文描述: WAN PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP64
封装: TQFP-64
文件页数: 20/127页
文件大小: 868K
代理商: IDT82V3255DK
IDT82V3255
WAN PLL
Functional Description
20
June 19, 2006
3.5
INPUT CLOCK QUALITY MONITORING
The qualities of all the input clocks are always monitored in the fol-
lowing aspects:
Activity
Frequency
The qualified clocks are available for T0/T4 DPLL selection. The T0
and T4 selected input clocks have to be monitored further. Refer to
Chapter 3.7 Selected Input Clock Monitoring
for details.
3.5.1
ACTIVITY MONITORING
Activity is monitored by using an internal leaky bucket accumulator,
as shown in
Figure 4
.
Each input clock is assigned an internal leaky bucket accumulator.
The input clock is monitored for each period of 128 ms and the internal
leaky bucket accumulator increases by 1 when an event is detected; it
decreases by 1 if no event is detected within the period set by the decay
rate. The event is that an input clock drifts outside (>) ±500 ppm with
respect to the master clock within a 128 ms period.
There are four configurations (0 - 3) for a leaky bucket accumulator.
The leaky bucket configuration for an input clock is selected by the cor-
responding BUCKET_SEL[1:0] bits. Each leaky bucket configuration
consists of four elements: upper threshold, lower threshold, bucket size
and decay rate.
The bucket size is the capability of the accumulator. If the number of
the accumulated events reach the bucket size, the accumulator will stop
increasing even if further events are detected. The upper threshold is a
point above which a no-activity alarm is raised. The lower threshold is a
point below which the no-activity alarm is cleared. The decay rate is a
certain period during which the accumulator decreases by 1 if no event
is detected.
The leaky bucket configuration is programmed by one of four groups
of register bits: the BUCKET_SIZE_n_DATA[7:0]
bits,
the
UPPER_
THRESHOLD_n_DATA[7:0]
bits,
DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’
is 0 ~ 3.
the
LOWER_THRESHOLD_n_
The no-activity alarm status of the input clock is indicated by the
INn_CMOS_NO_ACTIVITY_ALARM bit (n = 1, 2, or 3) /
INn_DIFF_NO_ACTIVITY_ALARM bit (n = 1 or 2).
The input clock with a no-activity alarm is disqualified for clock selec-
tion for T0/T4 DPLL.
Figure 4. Input Clock Activity Monitoring
Input Clock
Leaky Bucket Accumulator
No-activity Alarm Indication
Decay
Rate
Bucket Size
Upper Threshold
Lower Threshold
0
clock signal with no event
clock signal with events
相关PDF资料
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IDT82V3255DKG WAN PLL
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