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参数资料
型号： IDT82V3255DK
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 通信及网络
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封装： TQFP-64
文件页数： 36/127页
文件大小： 868K
代理商： IDT82V3255DK
IDT82V3255
WAN PLL
Functional Description
36
June 19, 2006
3.12
T0 / T4 APLL
A T0 APLL and a T4 APLL are provided for a better jitter and wander
performance of the device output clocks.
The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0]
/ T4_APLL_BW[1:0] bits respectively. The lower the bandwidth is, the
better the jitter and wander performance of the T0/T4 APLL output are.
The input of the T0/T4 APLL can be derived from one of the T0 and
T4 DPLL outputs, as selected by the T0_APLL_PATH[3:0] /
T4_APLL_PATH[3:0] bits respectively.
Both the APLL and DPLL outputs are provided for selection for the
device output.
3.13
OUTPUT CLOCKS & FRAME SYNC SIGNALS
The device supports 2 output clocks and 2 frame sync output signals
altogether.
3.13.1
OUTPUT CLOCKS
The device provides 2 output clocks.
OUT1 outputs a PECL or LVDS signal, as selected by the
OUT1_PECL_LVDS bit. OUT2 outputs a CMOS signal.
The outputs on OUT1 and OUT2 are variable, depending on the sig-
nals derived from the T0/T4 DPLL and T0/T4 APLL outputs, and the cor-
responding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). The derived signal
can be from the T0/T4 DPLL and T0/T4 APLL outputs, as selected by
the corresponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). If the signal is
derived from one of the T0/T4 DPLL outputs, please refer to
Table 25
for
the output frequency. If the signal is derived from the T0/T4 APLL output,
please refer to
Table 26
for the output frequency.
The outputs on OUT1 and OUT2 can be inverted, as determined by
the corresponding OUTn_INV bit (n = 1 or 2).
Both the output clocks derived from T0/T4 selected input clock are
aligned with the T0/T4 selected input clock respectively every 125 μs
period.
Table 24: Related Bit / Register in Chapter 3.12
Bit
Register
Address (Hex)
T0_APLL_BW[1:0]
T4_APLL_BW[1:0]
T0_APLL_PATH[3:0]
T4_APLL_PATH[3:0]
T0_T4_APLL_BW_CNFG
6A
T0_DPLL_APLL_PATH_CNFG
T4_DPLL_APLL_PATH_CNFG
55
60
Table 25: Outputs on OUT1 & OUT2 if Derived from T0/T4 DPLL Outputs
OUTn_DIVIDER[3:0]
(Output Divider)
1
outputs on OUT1 & OUT2 if derived from T0/T4 DPLL outputs
2
77.76 MHz
12E1
16E1
24T1
16T1
E3
T3
GSM
(26 MHz)
OBSAI
(30.72 MHz)
GPS
(40 MHz)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Output is disabled (output low).
12E1
6E1
3E1
2E1
16E1
8E1
4E1
24T1
12T1
6T1
4T1
3T1
2T1
16T1
8T1
4T1
E3
T3
13 MHz
15.36 MHz
20
10
2E1
2T1
5
E1
E1
T1
T1
64 kHz
8 kHz
2 kHz
400 Hz
1Hz
Output is disabled (output high).
Note:
1.
n = 1 or 2.
Each output is assigned a frequency divider
.
2. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is reserved.
相关PDF资料
PDF描述
IDT82V3255DKG WAN PLL
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相关代理商/技术参数
参数描述
IDT82V3255DKG 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT
IDT82V3255DKG8 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT
IDT82V3255EDGBLANK 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255TF 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255TFBLANK 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
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