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参数资料
型号： IDT82V3255DK
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 通信及网络
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封装： TQFP-64
文件页数： 22/127页
文件大小： 868K
代理商： IDT82V3255DK
IDT82V3255
WAN PLL
Functional Description
22
June 19, 2006
3.6
T0 / T4 DPLL INPUT CLOCK SELECTION
An input clock is selected for T0 DPLL and for T4 DPLL respectively.
For T0 path, the EXT_SW bit and the T0_INPUT_SEL[3:0] bits deter-
mine the input clock selection, as shown in
Table 6
:
For T4 path, the T4 DPLL may lock to a T0 DPLL output or lock inde-
pendently from T0 path, as determined by the T4_LOCK_T0 bit. When
the T4 DPLL locks to the T0 DPLL output, the T4 selected input clock is
a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path (refer to
Chapter 3.11.5.1 T0 Path
), as determined by the T0_FOR_T4 bit. When
the T4 path locks independently from the T0 path, the T4 DPLL input
clock selection is determined by the T4_INPUT_SEL[3:0] bits. Refer to
Table 7
:
External Fast selection is done between IN1_CMOS/IN1_DIFF and
IN2_CMOS/IN2_DIFF pairs.
Forced selection is done by setting the related registers.
Automatic selection is done based on the results of input clocks qual-
ity monitoring and the related registers configuration.
The selected input clock is attempted to be locked in T0/T4 DPLL.
3.6.1
EXTERNAL FAST SELECTION (T0 ONLY)
The External Fast selection is supported by T0 path only. In External
Fast selection, only IN1_CMOS/IN1_DIFF and IN2_CMOS/IN2_DIFF
pairs are available for selection. Refer to
Figure 5
. The results of input
clocks quality monitoring (refer to
Chapter 3.5 Input Clock Quality Moni-
toring
) do not affect input clock selection.
The T0 input clock selection is determined by the FF_SRCSW pin
after reset (this pin determines the default value of the EXT_SW bit dur-
ing
reset,
refer
to
Chapter 2
IN1_CMOS_SEL_PRIORITY[3:0]
IN2_CMOS_SEL_PRIORITY[3:0] bits, as shown in
Figure 5
and
Table 8
:
Pin
Description
),
and
the
the
bits
Figure 5. External Fast Selection
Table 6: Input Clock Selection for T0 Path
Control Bits
Input Clock Selection
EXT_SW
T0_INPUT_SEL[3:0]
1
don’t-care
other than 0000
0000
External Fast selection
Forced selection
Automatic selection
0
Table 7: Input Clock Selection for T4 Path
Control Bits - T4_INPUT_SEL[3:0]
Input Clock Selection
other than 0000
0000
Forced selection
Automatic selection
FF_SRCSW pin
IN1_CMOS
IN1_DIFF
IN2_CMOS
IN2_DIFF
IN1_CMOS_SEL_PRIORITY[3:0] bits
IN2_CMOS_SEL_PRIORITY[3:0] bits
attempted to be
locked in T0 DPLL
Table 8: External Fast Selection
Control Pin & Bits
the Selected Input Clock
FF_SRCSW (after reset)
IN1_CMOS_SEL_PRIORITY[3:0]
IN2_CMOS_SEL_PRIORITY[3:0]
high
0000
don’t-care
IN1_DIFF
IN1_CMOS
IN2_DIFF
IN2_CMOS
other than 0000
low
don’t-care
0000
other than 0000
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PDF描述
IDT82V3255DKG WAN PLL
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参数描述
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