参数资料
| 型号： | IP-ASI |
| 厂商： | Altera |
| 文件页数： | 12/27页 |
| 文件大小： | 0K |
| 描述： | IP VIDEO INTERFACE - ASI |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 数字视频广播用接收器/收发器 |
| 许可证： | 初始许可证 |
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Chapter 2: Getting Started
Design Flow
Table 2–1 describes the generated files and other files that may be in your project
directory. The names and types of files specified in the summary vary based on
whether you created your design with VHDL or Verilog HDL.
Table 2–1. Generated Files
2–3
File Name
<variation name> .v or .vhd
<variation name> .cmp
<variation name> .bsf
< variation name > .html
<variation name> .ppf
<variation name> .vo or .vho
< variation name > _bb.v
<variation name> .qip
Description
A MegaCore function variation file, which defines a VHDL or Verilog HDL
description of the custom MegaCore function. Instantiate the entity defined by
this file inside of your design. Include this file when compiling your design in
the Quartus II software.
A VHDL component declaration file for the MegaCore function variation. Add
the contents of this file to any VHDL architecture that instantiates the
MegaCore function.
Quartus II symbol file for the MegaCore function variation. You can use this file
in the Quartus II block diagram editor.
MegaCore function report file.
This XML file describes the MegaCore pin attributes to the Quartus II Pin
Planner. MegaCore pin attributes include pin direction, location, I/O standard
assignments, and drive strength. If you launch IP Toolbench outside of the Pin
Planner application, you must explicitly load this file to use Pin Planner.
VHDL or Verilog HDL IP functional simulation model.
A Verilog HDL black-box file for the MegaCore function variation. Use this file
when using a third-party EDA tool to synthesize your design.
Contains Quartus II project information for your MegaCore function variations.
You can now integrate your custom MegaCore function variation into your design
and simulate and compile.
Simulate the Design
This section describes the following simulation techniques:
■
■
■
Simulate with IP Functional Simulation Models
You can simulate your design using the MegaWizard-generated VHDL and Verilog
HDL IP functional simulation models.
You can use the IP functional simulation model with any Altera-supported VHDL or
Verilog HDL simulator. To use the IP functional simulation model, create a suitable
testbench.
f For more information on IP functional simulation models, refer to the Simulating
January 2014
Altera Corporation
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| IP-ED8B10B | IP 8B10B ENCODER/DECODER |
| IP-FFT | IP FFT/IFFT |
| IP-FIR | IP FIR COMPILER |
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPB009N03L G | 功能描述:MOSFET OptiMOS 3 PWR TRANS 30V 180A RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| IPB009N03LG | 制造商:Infineon Technologies AG 功能描述:MOSFET N-Ch 30V 180A OptiMOS3 TO263-7 |
| IPB009N03LGATMA1 | 制造商:Infineon Technologies AG 功能描述:Trans MOSFET N-CH 30V 180A 7-Pin(6+Tab) TO-263 制造商:Infineon Technologies AG 功能描述:N-KANAL POWER MOS - Tape and Reel 制造商:Infineon Technologies AG 功能描述:MOSFET N-CH 30V 180A TO263-7 |
| IPB010N06N | 功能描述:MOSFET 60V TO-263 RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| IPB010N06NATMA1 | 功能描述:MOSFET MV POWER MOS RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
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