参数资料
型号: IP-ASI
厂商: Altera
文件页数: 17/27页
文件大小: 0K
描述: IP VIDEO INTERFACE - ASI
标准包装: 1
系列: *
类型: MegaCore
功能: 数字视频广播用接收器/收发器
许可证: 初始许可证
4–2
Chapter 4: Functional Description
Receiver
Serializer
The serializer converts a 10-bit parallel word into a serial data output format. A 10-bit
shift register loaded at the word rate from the encoder and unloaded at the bit rate of
the LVDS output buffer is implemented for that function. You should use a PLL that
multiplies a 27-MHz reference clock by ten to provide the bit-rate clock and enables
jitter-controlled ASI transmit serialization.
GX Transceivers
For GX-based devices, in the MegaWizard Plug-In Manager you can select either a
soft-logic transceiver or a GX transceiver. If you are using GX transceivers, the
transmitter has a FIFO buffer, oversampler, and a transceiver, which replace the
soft-logic serializer.
f For more information on the Stratix IV transceiver, refer to the Stratix IV Device
Receiver
The receiver comprises the following elements:
Figure 4–2 shows the ASI receiver.
Figure 4–2. ASI Receiver
337.5-MHz
135 MHz
337.5-MHz
Clock -90 o
Clock
Protocol Blocks
Clock
Transceiver
Deserializer
Transceiver
10
Oversampling
Interface
10
Word
Aligner
10
8B10B
Decoder
8
Sync.
FSM
Packet
Sync.
Parallel
Data
Out
Soft-logic transceiver implementations only
GX-based devices only
LVDS I/O
Serial Data
Transceiver
The transceiver can be either a deserializer for soft-logic implementations or a GX
transceiver.
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
January 2014 Altera Corporation
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