参数资料
| 型号： | IP-ASI |
| 厂商： | Altera |
| 文件页数： | 20/27页 |
| 文件大小： | 0K |
| 描述： | IP VIDEO INTERFACE - ASI |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 数字视频广播用接收器/收发器 |
| 许可证： | 初始许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页当前第20页第21页第22页第23页第24页第25页第26页第27页
Chapter 4: Functional Description
4–5
Testbench
Testbench
The testbench instantiates two ASI MegaCore functions—one ASI transmitter, one
ASI receiver.
To test a realistic ASI link, an ASI packet generator creates packets that are sent from
the instantiation of the ASI transmitter to the instantiation of the ASI receiver. A
random serial data delay generator is inserted on the way to mimic random jitter on
the link. The transmitter and receiver are clocked with asynchronous clock sources—
the frequencies differ by 200 ppm, which maximizes the stress that the ASI receiver
sees and is similar to a real link.
Signals
Table 4–1 shows the signals.
Table 4–1. Signals (Part 1 of 2)
Signal
asi_rx
cal_blk_clk
gxb_powerdown (1)
reconfig_clk (1) (2)
reconfig_togxb[3:0] (1) (2)
rst
rx_clk135
rx_protocol_in[9:0]
rx_protocol_in_valid
rx_serial_clk
rx_serial_clk90
tx_clk270
tx_clk135
tx_data[7:0]
tx_en
tx_refclk
tx_serdes_in[9:0]
asi_tx
reconfig_fromgxb[16:0] (1) (2)
rx_data[7:0]
rx_data_clk
rx_serdes_out[9:0]
rx_serdes_out_valid
Direction
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Description
ASI input.
Calibration clock for hard transceiver.
Transceiver block reset and power down. This signal of all the
instances that are to be combined into a single transceiver block
must be connected to a single point; for example, the same input
pin or same logic.
Clock input for the embedded transceiver instance.
Data input for the embedded transceiver instance.
Reset.
135-MHz clock from external PLL.
Protocol input (for split SERDES/protocol).
Valid signal for rx_protocol_in .
337.5-MHz clock from external PLL.
337.5-MHz clock from external PLL with + 90 ? phase shift.
270-MHz clock from external PLL.
135-MHz clock from external PLL (only for hard SERDES).
TS parallel data input into encoder.
Transmit enable. Assert to indicate valid data on tx_data .
27-MHz reference clock for transmitter.
Direct input to transceiver block for split protocol/tranceiver mode.
ASI output.
Data output from the embedded transceiver instance.
Decoded parallel TS data out of receiver.
135-MHz parallel clock, which you can use to clock
rx_data[7:0] .
Raw data from transceiver block before decoding.
Valid signal out of the transceiver.
January 2014
Altera Corporation
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| IP-ED8B10B | IP 8B10B ENCODER/DECODER |
| IP-FFT | IP FFT/IFFT |
| IP-FIR | IP FIR COMPILER |
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPB009N03L G | 功能描述:MOSFET OptiMOS 3 PWR TRANS 30V 180A RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| IPB009N03LG | 制造商:Infineon Technologies AG 功能描述:MOSFET N-Ch 30V 180A OptiMOS3 TO263-7 |
| IPB009N03LGATMA1 | 制造商:Infineon Technologies AG 功能描述:Trans MOSFET N-CH 30V 180A 7-Pin(6+Tab) TO-263 制造商:Infineon Technologies AG 功能描述:N-KANAL POWER MOS - Tape and Reel 制造商:Infineon Technologies AG 功能描述:MOSFET N-CH 30V 180A TO263-7 |
| IPB010N06N | 功能描述:MOSFET 60V TO-263 RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| IPB010N06NATMA1 | 功能描述:MOSFET MV POWER MOS RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
发布紧急采购，3分钟左右您将得到回复。