参数资料
| 型号： | IP-RSDEC |
| 厂商： | Altera |
| 文件页数： | 11/38页 |
| 文件大小： | 0K |
| 描述： | IP REED-SOLOMON DECODER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Reed-Solomon 解码器 |
| 许可证： | 初始许可证 |
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2. Getting Started
Design Flows
The RS Compiler supports the following design flows:
■
■
DSP Builder : Use this flow if you want to create a DSP Builder model that
includes a RS Compiler variation.
MegaWizard? Plug-In Manager : Use this flow if you would like to create a RS
Compiler variation that you can instantiate manually in your design.
parameterization provides the same options in each flow and is described in
“Parameterize the MegaCore Function” on page 2–3 .
After parameterizing and simulating a design in either of these flows, you can
compile the completed design in the Quartus II software.
DSP Builder Flow
Altera’s DSP Builder product shortens digital signal processing (DSP) design cycles
by helping you create the hardware representation of a DSP design in an
algorithm-friendly development environment.
DSP Builder integrates the algorithm development, simulation, and verification
capabilities of The MathWorks MATLAB ? and Simulink ? system-level design tools
with Altera Quartus II software and third-party synthesis and simulation tools. You
can combine existing Simulink blocks with Altera DSP Builder blocks and MegaCore
function variation blocks to verify system-level specifications and perform
simulation.
In DSP Builder, a Simulink symbol for the MegaCore function appears in the
MegaCore Functions library of the Altera DSP Builder Blockset in the Simulink library
browser.
To use the RS Compiler in the MATLAB/Simulink environment, follow these steps:
1. Create a new Simulink model.
2. Select the reed_solomon_ < version > block from the MegaCore Functions library in
the Simulink Library Browser, add it to your model, and give the block a unique
name.
example of setting parameters for the RS Compiler, refer to “Parameterize the
MegaCore Function” on page 2–3 .
4. Click Finish in the parameter editor to complete the parameterization and
generate your RS Compiler MegaCore function variation. For information about
the generated files, refer to Table 2–1 on page 2–8 .
5. Connect your RS Compiler MegaCore function variation to the other blocks in
your model.
November 2013
Altera Corporation
Reed-Solomon Compiler
User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
| IP-VITERBI/SS | IP VITERBI LOW-SPEED |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SDI | 功能描述:开发软件 Video Interface SDI MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SDI-II | 功能描述:开发软件 SDI II Video MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SDRAM/DDR | 功能描述:开发软件 DDR SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SDRAM/DDR2 | 功能描述:开发软件 DDR2 SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SDRAM/DDR3 | 功能描述:开发软件 DDR3 SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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