参数资料
| 型号： | IP-RSDEC |
| 厂商： | Altera |
| 文件页数： | 28/38页 |
| 文件大小： | 0K |
| 描述： | IP REED-SOLOMON DECODER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Reed-Solomon 解码器 |
| 许可证： | 初始许可证 |
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3–8
Chapter 3: Functional Description
Signals
Table 3–3 shows the RS codeword parameters.
Table 3–3. RS Codeword Parameters
Parameter
Number of bits per
symbol
Number of symbols per
codeword
Number of check symbols
per codeword
Range
3 to 12
5 to (2 m – 1)
2 to min(128, N – 1)
Range
(Continuous)
6 to 12
7( R + 1) to 2 m – 1
4 to N /7 – 1
Description
Specifies the number of bits per symbol ( m ).
Specifies the total number of symbols per
codeword ( N ).
Specifies the number of check symbols per
codeword ( R )
Field polynomial
First root of generator
polynomial
Root spacing in generator
polynomial
Any valid polynomial
0 to (2 m – 2)
Any valid root space
(1)
(1)
Specifies the primitive polynomial defining the
Galois field.
Specifies the first root of the generator polynomial
( i 0 ).
Specifies the minimum distance between roots in
the generator polynomial ( a ).
Notes to Table 3–3 :
(1) IP Toolbench allows you to select only legal values. For m > 8, not all legal values of the field polynomials and rootspace are present in IP
Toolbench. If you cannot find your intended field polynomial or rootspace in the IP Toolbench list, contact Altera MySupport.
Signals
Table 3–4 shows the global signals.
Table 3–4. Global Signals
Name
clk
reset
Description
clk is the main system clock. The whole MegaCore function operates on the rising edge of clk .
Reset. The entire decoder is asynchronously reset when reset is asserted high. The reset signal resets the
entire system. The reset signal must be de-asserted synchronously with respect to the rising edge of clk .
Reed-Solomon Compiler
User Guide
November 2013 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
| IP-VITERBI/SS | IP VITERBI LOW-SPEED |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SDI | 功能描述:开发软件 Video Interface SDI MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SDI-II | 功能描述:开发软件 SDI II Video MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SDRAM/DDR | 功能描述:开发软件 DDR SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SDRAM/DDR2 | 功能描述:开发软件 DDR2 SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SDRAM/DDR3 | 功能描述:开发软件 DDR3 SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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