参数资料
| 型号： | IP-RSDEC |
| 厂商： | Altera |
| 文件页数： | 29/38页 |
| 文件大小： | 0K |
| 描述： | IP REED-SOLOMON DECODER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Reed-Solomon 解码器 |
| 许可证： | 初始许可证 |
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Chapter 3: Functional Description
Signals
Table 3–5 shows the Avalon-ST sink (data input) interface.
Table 3–5. Avalon-ST Sink Interface
3–9
Name
Avalon-ST
Type
Direction
Description
Data transfer enable signal. sink_ena is driven by the sink interface and controls
the flow of data across the interface. sink_ena behaves as a read enable from sink
to source. When the source observes sink_ena asserted on the clk rising edge it
sink_ena
ena
Output
drives, on the following clk rising edge, the Avalon-ST data interface signals and
asserts val , if data is available. The sink interface captures the data interface
signals on the following clk rising edge. If the source is unable to provide new
data, it de-asserts val for one or more clock cycles until it is prepared to drive valid
data interface signals.
Data valid signal. sink_val indicates the validity of the data signals. sink_val is
updated on every clock edge where sink_ena is asserted. sink_val and the dat
bus hold their current value if sink_ena is de-asserted. When sink_val is
sink_val
val
Input
asserted, the Avalon-ST data interface signals are valid. When sink_val is de-
asserted, the Avalon-ST data interface signals are invalid and must be disregarded.
To determine whether new data has been received, the sink interface qualifies the
sink_val signal with the previous state of the sink_ena signal.
Start of packet (codeword) signal. sop delineates the codeword boundaries on the
sink_sop
sop
Input
rsin bus. When sink_ sop is high, the start of the packet is present on the rsin
bus. sink_ sop is asserted on the first transfer of every codeword.
End of packet (codeword) signal. sink_ eop delineates the packet boundaries on the
sink_eop
eop
Input
rsin bus. When sink_ eop is high, the end of the packet is present on the dat bus.
sink_ eop is asserted on the last transfer of every packet.
rsin[m:1]
eras_sym
data
data
Input
Data input for each codeword, symbol by symbol. Valid only when sink_val is
asserted.
When asserted, the symbol in rsin[] is marked as an erasure. Valid only for the
decoder with Erasures-supporting decoder option.
Table 3–6 shows the Avalon-ST source (data output) interface.
Table 3–6. Avalon-ST Source Interface (Part 1 of 2)
Name
Avalon-ST
Type
Direction
Description
Data transfer enable signal. source_ena is driven by the sink interface and
controls the flow of data across the interface. ena behaves as a read enable from
sink to source. When the source interface observes source_ena asserted on the
clk rising edge it drives, on the following clk rising edge, the Avalon-ST data
source_ena
ena
Input
interface signals and asserts source_val when data from sink interface is
available. The sink interface captures the data interface signals on the following
clk rising edge. If this source is unable to provide new data, it de-asserts
source_val for one or more clock cycles until it is prepared to drive valid data
interface signals.
source_val
source_sop
source_eop
November 2013
val
sop
eop
Altera Corporation
Output
Output
Output
Data valid signal. source_val is asserted high, whenever there is a valid output on
rsout ; it is de-asserted when there is no valid output on rsout .
Start of packet (codeword) signal.
End of packet (codeword) signal.
Reed-Solomon Compiler
User Guide
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PDF描述 |
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| IPR-SDI | 功能描述:开发软件 Video Interface SDI MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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| IPR-SDRAM/DDR | 功能描述:开发软件 DDR SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SDRAM/DDR2 | 功能描述:开发软件 DDR2 SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SDRAM/DDR3 | 功能描述:开发软件 DDR3 SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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