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| 型号： | IPR-NCO |
| 厂商： | Altera |
| 文件页数： | 31/54页 |
| 文件大小： | 0K |
| 描述： | IP NCO COMPILER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 数控振荡器编译器 |
| 许可证： | 续用许可证 |
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Chapter 3: Parameter Settings
Parameter Descriptions
Table 3–2. NCO MegaCore Function Implementation Page (Part 2 of 2)
3–9
Parameter
Device Family Target
Number of Channels
Number of Bands
CORDIC Implementation
Multiplier-Based Architecture
Clock Cycles Per Output
Value
Stratix IV, Stratix III,
Stratix II, Stratix II GX,
Arria GX, Stratix,
Stratix GX, Cyclone III,
Cyclone II, Cyclone
1–8, Default = 1
1–16, Default = 1
Parallel, Serial
Logic Elements,
Dedicated Multipliers
1, 2, Default = 1
Description
Displays the target device family. The target device family is
preselected by the value specified in the Quartus II or DSP Builder
software. The HDL that is generated for your MegaCore function
variation may be incorrect if you change the device family target in
IP Toolbench.
Select the number of channels when you want to implement a
multi-channel NCO.
Select a number of bands greater than 1 to enable frequency
hopping. Frequency hopping is not supported in the serial CORDIC
architecture.
When the CORDIC generation algorithm is selected on the
Parameters page, you can select a parallel (one output per clock
cycle) or serial (one output per 18 clock cycles) implementation.
When the multiplier-based algorithm is selected on the Parameters
page, you can select logic elements or dedicated multipliers and
select the number of clock cycles per output. This option is not
available if you target the Cyclone device family.
When the multiplier-based algorithm is selected on the Parameters
page, you can select 1 or 2 clock cycles per output.
Table 3–3 shows the parameters that are displayed in the Resource Estimate page.
Table 3–3. NCO MegaCore Function Resource Estimate Page
Parameter
Description
Number of ALUTs/LEs
Number of Memory Bits
Displays the number of adaptive look-up tables or logic elements.
Displays the number of memory bits.
(1)
Number of M9Ks/M4Ks
Number of 9-bit DSP Elements
Displays the number of M20K, M9K, or M4K RAM blocks.
Displays the number of 9-bit DSP elements.
(2)
Notes to Table 3–3 :
(1) Stratix GX, Stratix, Cyclone III, Cyclone II and Cyclone devices use LEs; all other devices use ALUTs.
(2) Stratix V devices use M20K RAM blocks; Stratix IV, Stratix III, and Cyclone III devices use M9K RAM blocks; all other devices use M4K blocks.
November 2013
Altera Corporation
NCO MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-NIOS | 功能描述:开发软件 Nios II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPROBER 520 | 制造商:TTi-Thurlby Thandar Instruments 功能描述:Bulk 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, POSITIONAL, ON PCB TRACK 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, 5MHZ, 2M; Test Probe Ratio:-; Connector Type A:-; Connector Type B:-; Lead Length:2m; Bandwidth:5MHz; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: NA |
| IPR-PCI/MT32 | 功能描述:开发软件 PCI 32b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/MT64 | 功能描述:开发软件 PCI 64b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/T32 | 功能描述:开发软件 PCI 32-bit Target MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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