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| 型号： | IPR-NCO |
| 厂商： | Altera |
| 文件页数： | 44/54页 |
| 文件大小： | 0K |
| 描述： | IP NCO COMPILER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 数控振荡器编译器 |
| 许可证： | 续用许可证 |
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4–12
Chapter 4: Functional Description
Signals
Figure 4–8 shows the timing diagram for a multi-channel NCO in the case where the
number of channels, M is set to 4. The input phase increments for each channel, P k are
interleaved and loaded sequentially.
Figure 4–8. Multi-Channel NCO Timing Diagram
The phase increment for channel 0 is the first value read in on the rising edge of the
clock following the de-assertion of reset_n (assuming clken is asserted) followed
by the phase increments for the next ( M -1) channels. The output signal out_valid is
asserted when the first valid sine and cosine outputs for channel 0, S 0 , C 0 , respectively
are available.
The output values S k and C k corresponding to channels 1 through ( M -1) are output
sequentially by the NCO. The outputs are interleaved so that a new output sample for
channel k is available every M cycles.
Signals
The NCO MegaCore function supports the input and output signals shown in
Table 4–4 .
Table 4–4. NCO MegaCore FunctionSignals (Part 1 of 2)
Signal
address[2:0]
clk
clken
freq_mod_i [F-1:0]
freq_sel[log 2 N-1:0]
phase_mod_i [P-1:0]
phi_inc_i [A-1:0]
reset_n
write_sig
fcos_o [M-1:0]
NCO MegaCore Function
User Guide
Direction
Input
Input
Input
Input
input
Input
Input
Input
Input
Output
Description
Address of the 16 phase increment registers when frequency hopping is enabled.
Clock.
Active-high clock enable.
Optional frequency modulation input. You can specify the modulator resolution F
in IP Toolbench.
Use to select one of the phase increment registers (that is to select the hopping
frequencies), when frequency hopping is enabled. N is the depth.
Optional phase modulation input. You can specify the modulator precision P in IP
Toolbench.
Input phase increment. You can specify the accumulator precision A in IP
Toolbench.
Active-low asynchronous reset.
Active-high write signal when frequency hopping is enabled.
Optional output cosine value (when dual output is selected). You can specify the
magnitude precision M in IP Toolbench.
November 2013 Altera Corporation
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| IPR-NIOS | 功能描述:开发软件 Nios II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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| IPR-PCI/MT32 | 功能描述:开发软件 PCI 32b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/MT64 | 功能描述:开发软件 PCI 64b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/T32 | 功能描述:开发软件 PCI 32-bit Target MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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