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| 型号： | IPR-NCO |
| 厂商： | Altera |
| 文件页数： | 42/54页 |
| 文件大小： | 0K |
| 描述： | IP NCO COMPILER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 数控振荡器编译器 |
| 许可证： | 续用许可证 |
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4–10
Chapter 4: Functional Description
Functional Description
Timing Diagrams
Figure 4–5 shows the timing with a single clock cycle per output sample.
Figure 4–5. Single-Cycle Per Output Timing Diagram
clk
clken
phi_inc_i 42949673
reset_n
fsin_0 0
-3 2057 41... 61.... 8148 10... 12... 13.... 15...
fcos_0 0
32767
32... 32... 32... 32... 31... 31... 30... 29... 28
out_ v alid
All NCO architectures—except for serial CORDIC and multi-cycle multiplier-based
architectures—output a sample every clock cycle. After the clock enable is asserted,
the oscillator outputs the sinusoidal samples at a rate of one sample per clock cycle,
following an initial latency of L clock cycles. The exact value of L varies across
architectures and parameterizations.
1
For the non-single-cycle per output architectures, the optional phase and frequency
modulation inputs need to be valid at the same time as the corresponding phase
increment value. The values should be sampled every 2 cycles for the two-cycle
multiplier-based architecture and every N cycles for the serial CORDIC architecture,
Figure 4–6 shows the timing diagram for a two-cycle multiplier-based NCO
architecture.
Figure 4–6. Two-Cycle Multiplier-Based Architecture Timing Diagram
clk
clken
phi_inc_i 85899346
reset_n
out_ v alid
fsin_0 0
-3 41... 81... 12.... 15... 19... 22... 25... 27... 29... 31... 32.... 32... 32... 32... 31... 29...
fcos_0 0
32766
32... 32... 31... 30... 28... 26... 23... 20... 17... 13... 10... 61.... 20... -2... -6... -1... -1...
After the clock enable is asserted, the oscillator outputs the sinusoidal samples at a
rate of one sample for every two clock cycles, following an initial latency of L clock
cycles. The exact value of L depends on the parameters that you set.
NCO MegaCore Function
User Guide
November 2013 Altera Corporation
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相关代理商/技术参数 |
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|---|---|
| IPR-NIOS | 功能描述:开发软件 Nios II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPROBER 520 | 制造商:TTi-Thurlby Thandar Instruments 功能描述:Bulk 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, POSITIONAL, ON PCB TRACK 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, 5MHZ, 2M; Test Probe Ratio:-; Connector Type A:-; Connector Type B:-; Lead Length:2m; Bandwidth:5MHz; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: NA |
| IPR-PCI/MT32 | 功能描述:开发软件 PCI 32b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/MT64 | 功能描述:开发软件 PCI 64b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/T32 | 功能描述:开发软件 PCI 32-bit Target MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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