参数资料
型号: IPR-NCO
厂商: Altera
文件页数: 40/54页
文件大小: 0K
描述: IP NCO COMPILER RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: 数控振荡器编译器
许可证: 续用许可证
4–8
Chapter 4: Functional Description
Functional Description
Phase Dithering
All digital sinusoidal synthesizers suffer from the effects of finite precision, which
manifests itself as spurs in the spectral representation of the output sinusoid. Because
of angular precision limitations, the derived phase of the oscillator tends to be
periodic in time and contributes to the presence of spurious frequencies. You can
reduce the noise at these frequencies by introducing a random signal of suitable
variance into the derived phase, thereby reducing the likelihood of identical values
over time. Adding noise into the data path raises the overall noise level within the
oscillator, but tends to reduce the noise localization and can provide significant
improvement in SFDR.
The extent to which you can reduce spur levels is dependent on many factors. The
likelihood of repetition of derived phase values and resulting spurs, for a given
angular precision, is closely linked to the ratio of the clock frequency to the desired
output frequency. An integral ratio clearly results in high-level spurious frequencies,
while an irrational relationship is less likely to result in highly correlated noise at
harmonic frequencies.
The Altera NCO MegaCore function allows you to finely tune the variance of the
dither sequence for your chosen algorithm, specified precision, and clock frequency to
output frequency ratio, and dynamically view the effects on the output spectrum
graphically.
For an example using phase dithering and its effect on the spectrum of the output
signal, refer to the “Multichannel Design” on page A–1 .
Multi-Channel NCOs
The NCO MegaCore function allows you to implement multi-channel NCOs. This
allows for multiple sinusoids of independent frequency and phase to be generated at
a very low cost in additional resources. The resulting waveforms have an output
sample-rate of f clk / M where M is the number of channels. You can select 1 to 8
channels.
Multi-channel implementations are available for all single-cycle generation
algorithms. The input phase increment, frequency modulation value and phase
modulation input are input sequentially to the NCO with the input values
corresponding to channel 0 first and channel ( M –1) last. The inputs to channel 0
should be input on the rising clock edge immediately following the de-assertion of the
NCO reset.
On the output side, the first output sample for channel 0 is output concurrent with the
assertion of out_valid and the remaining outputs for channels 1 to ( M –1) are output
sequentially. Refer to “Multi-Channel NCO Timing Diagram” on page 4–12 for details
of how the data is provided to and received from a multi-channel NCO.
If a multi-channel implementation is selected, the NCO MegaCore function generates
VHDL and Verilog test benches that time-division-multiplex the inputs into a single
stream and de-multiplex the output streams into their respective down-sampled
channelized outputs.
For an example of a multi-channel NCO, refer to “Multichannel Design” on page A–1 .
NCO MegaCore Function
User Guide
November 2013 Altera Corporation
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