- 您现在的位置：买卖IC网 > PDF目录16076 > IPR-NCO (Altera)IP NCO COMPILER RENEW PDF资料下载
参数资料
| 型号： | IPR-NCO |
| 厂商： | Altera |
| 文件页数： | 38/54页 |
| 文件大小： | 0K |
| 描述： | IP NCO COMPILER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 数控振荡器编译器 |
| 许可证： | 续用许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页当前第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页
4–6
Chapter 4: Functional Description
Functional Description
In an NCO, the CORDIC algorithm computes the sine and cosine of an input phase
value by iteratively shifting the phase angle to approximate the cartesian coordinate
values for the input angle. At the end of the CORDIC iteration, the x and y coordinates
for a given angle represent the cosine and sine of that angle, respectively ( Figure 4–3 ).
Figure 4–3. CORDIC Rotation for Sine & Cosine Calculation
y
d?
dy
sin ?
?
cos ?
x
dx
With the NCO MegaCore function, you can select parallel (unrolled) or serial
(iterative) CORDIC architectures:
■
■
You an use the parallel CORDIC architecture to create a very high-performance,
high-precision oscillator—implemented entirely in logic elements—with a
throughput of one output sample per clock cycle. With this architecture, there is a
new output value every clock cycle.
The serial CORDIC architecture uses fewer resources than the parallel CORDIC
architecture. However, its throughput is reduced by a factor equal to the
magnitude precision. For example, if you select a magnitude precision of N bits in
the NCO MegaCore function, the output sample rate and the Nyquist frequency is
reduced by a factor of N . This architecture is implemented entirely in logic
elements and is useful if your design requires low frequency, high precision
waveforms. With this architecture, the adder stages are stored internally and a
new output value is produced every N clock cycles.
For more information about the parallel and serial CORDIC architectures, refer to
“Implementation Tab - CORDIC Algorithm” on page 3–5 .
Multiplier-Based Architecture
The multiplier-based architecture uses multipliers to reduce memory usage. You can
choose to implement the multipliers in either:
NCO MegaCore Function
User Guide
■
■
Logic elements (Cyclone series of devices) or combinational ALUTs (Stratix series
of devices).
Dedicated multiplier circuitry (for example, dedicated DSP blocks) in device
families that support this feature (Stratix V, Stratix IV, Stratix III, Stratix II, Stratix
GX, Stratix, or Arria GX devices).
November 2013 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| EMM06DRMT-S288 | CONN EDGECARD 12POS .156 EXTEND |
| VLCF4024T-470MR44-2 | INDUCTOR POWER 47UH 0.44A SMD |
| RP10-483.3SE/N | CONV DC/DC 10W 36-75VIN 3.3VOUT |
| M3YYK-2606R | IDC CABLE - MPD26K/MC26M/MPD26K |
| M3RRK-2606R | IDC CABLE - MPR26K/MC26M/MPR26K |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-NIOS | 功能描述:开发软件 Nios II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPROBER 520 | 制造商:TTi-Thurlby Thandar Instruments 功能描述:Bulk 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, POSITIONAL, ON PCB TRACK 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, 5MHZ, 2M; Test Probe Ratio:-; Connector Type A:-; Connector Type B:-; Lead Length:2m; Bandwidth:5MHz; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: NA |
| IPR-PCI/MT32 | 功能描述:开发软件 PCI 32b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/MT64 | 功能描述:开发软件 PCI 64b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/T32 | 功能描述:开发软件 PCI 32-bit Target MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。