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参数资料
| 型号： | IR3514MTRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 13/46页 |
| 文件大小： | 0K |
| 描述： | IC XPHASE3 CONTROL HYBRD 40-MLPQ |
| 产品变化通告： | (EP) Parts Discontinuation 25/May/2012 |
| 标准包装： | 1 |
| 系列： | XPhase3™ |
| 应用： | 处理器 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-MLPQ |
| 供应商设备封装： | 40-MLPQ（6x6） |
| 包装： | 标准包装 |
| 产品目录页面： | 1383 (CN2011-ZH PDF) |
| 其它名称： | IR3514MTRPBFDKR |
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The PWM block diagram of the xPHASE3
architecture is shown in Figure 5. Feed-forward voltage mode control
IR3514
SYSTEM THEORY OF OPERATION
PWM Control Method
TM
with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is
used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The
PWM ramp slope will change with the input voltage automatically compensating for changes in the input voltage.
The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace
voltage drop related to changes in load current.
IR3514 CONTROL IC
GATE DRIVE
VOLTAGE
VIN
CLOCK GENERATOR
CLKOUT
PHSOUT
CLKIN
CLK Q
IR3505 PHASE IC
VCC
VCCH
PHSOUT
PHSIN
PHSIN
EAIN
D
PWM
COMPARATOR
-
+
PWM
LATCH
S
RESET
DOMINANT
R
GATEH
SW
VCCL
CBST
COUT
VOSNS1+
VOUT1
GND
REMOTE SENSE
ENABLE
GATEL
AMPLIFIER
VOUT1
VID6
RAMP
DISCHARGE
BODY
BRAKING
COMPARATOR
PGND
VOSNS1-
CLAMP
VDAC1
ERROR
LGND
SHARE ADJUST
ERROR AMPLIFIER
AMPLIFIER
VDAC
EAOUT1
RCP1
CCP11
CCP12
RFB12
RFB11
ISHARE
3K
-
VID6
VID6
+
VID6
VID6 +
+
CURRENT
SENSE
AMPLIFIER
CSIN+
CSIN-
CCS
RCS
FB1
CFB1
DACIN
IFB1
Output 1 Only
IROSC
VDRP1 AMP
VDRP1
IIN1
CDRP1
RDRP1
PHSOUT
CLKIN
PHSIN
CLK Q
D
IR3505 PHASE IC
PWM
LATCH
S
VCC
VCCH
GATEH
CBST
PWM
COMPARATOR
RESET
DOMINANT
SW
EAIN
-
+
ENABLE
VID6
RAMP
DISCHARGE
R
BODY
BRAKING
COMPARATOR
VCCL
GATEL
PGND
CLAMP
SHARE ADJUST
ERROR AMPLIFIER
ISHARE
3K
-
VID6
VID6
+
CURRENT
SENSE
AMPLIFIER
CSIN+
VID6
VID6 +
+
CSIN-
CCS
RCS
DACIN
Figure 5 - PWM Block Diagram
Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 250 kHz to 9 MHZ
by an external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs.
The phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output
(PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is
connected to PHSIN of the second phase IC, etc. The last phase IC (PHSOUT) is connected back to PHSIN of the
control IC to complete the loop. During power up, the control IC sends out clock signals from both CLKOUT and
PHSOUT pins and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the
daisy chain loop. Figure 6 shows the phase timing for a four phase converter.
Page 13 of 46
10/30/2007
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