参数资料
型号: IR3514MTRPBF
厂商: International Rectifier
文件页数: 22/46页
文件大小: 0K
描述: IC XPHASE3 CONTROL HYBRD 40-MLPQ
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 1
系列: XPhase3™
应用: 处理器
安装类型: 表面贴装
封装/外壳: 40-MLPQ
供应商设备封装: 40-MLPQ(6x6)
包装: 标准包装
产品目录页面: 1383 (CN2011-ZH PDF)
其它名称: IR3514MTRPBFDKR
IR3514
Remote Voltage Sensing
VOSENX+ and VOSENX- are used for remote sensing and connected directly to the load. The remote sense
differential amplifiers with high speed, low input offset and low input bias current ensure accurate voltage sensing
and fast transient response.
Start-up Sequence
The IR3514 has a programmable soft-start function to limit the surge current during the converter start-up. A
capacitor connected between the SS/DEL X and LGND pins controls soft start timing, over-current protection delay
and hiccup mode timing. Constant current sources and sinks control the charge and discharge rates of the
SS/DEL X .
Figure 11 depicts the SVID start-up sequence. If the ENABLE input is asserted and there are no faults, the SS/DEL X
pin will begin charging, the pre-PWROK 2 bit Boot VID codes are read and stored, and both VDAC pins transition to
the pre-PWROK Boot VID code. The error amplifier output EAOUT X is clamped low until SS/DEL X reaches 1.4V.
The error amplifier will then regulate the converter’s output voltage to match the V(SS/DEL X )-1.4V offset until the
converter output reaches the 2-bit Boot VID code. The SS/DEL X voltage continues to increase until it rises above
the threshold of Delay Comparator where the VRRDY output is allowed to go high. The SVID interface is activated
upon PWROK assertion and the VDAC X along with the converter output voltage will change in response to any
SVID commands.
The PVI Single Plane Mode start-up sequence is the same as the SVID startup sequence with the exceptions that
only SS/DEL1 will be allowed to charge and there is no Boot VID voltage. PWROK is ignored.
The Error Amplifier output EAOUTx is clamped low until SS/DELx reaches 1.4V. The error amplifier will then
regulate the converter’s output voltage to match the SS/DELx voltage less the 1.4V offset until the converter output
reaches the pre-PWROK 2 bit metal VID code. The SS/DELx voltage continues to increase until it rises above the
threshold of Delay Comparator. The VRRDY output is then de-asserted (allowed to go high). Upon PWROK
assertion the SVID interface is activated and VDACx and converter output will change in response to any SVID
commands.
VCCL under voltage, over current, or a low signal on the ENABLE input immediately sets the fault latch, which
causes the EAOUT pin to drive low, thereby turning off the phase IC drivers. The VRRDY pin also drives low and
SS/DEL X discharges to 0.2V. If the fault has cleared, the fault latch will be reset by the SS/DEL X discharge
comparator allowing another soft start charge cycle to occur.
Other fault conditions, such as output over voltage, open VOSNS sense lines, or an open phase timing daisy chain
set a different group of fault latches that can only be reset by cycling VCCL power. These faults discharge
SS/DEL X , pull down EAOUT X and drive VRRDY low.
SVID OFF codes turn off the converter by discharging SS/DEL X and pulling down EAOUTx but do not drive VRRDY
low. Upon receipt of a non-off SVID code the converter will re-soft start and transition to the voltage represented by
the SVID code as shown in Figure 11.
The converter can be disabled by pulling the SS/DELx pins below 0.6V.
Page 22 of 46
10/30/2007
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