参数资料
型号: IR3514MTRPBF
厂商: International Rectifier
文件页数: 41/46页
文件大小: 0K
描述: IC XPHASE3 CONTROL HYBRD 40-MLPQ
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 1
系列: XPhase3™
应用: 处理器
安装类型: 表面贴装
封装/外壳: 40-MLPQ
供应商设备封装: 40-MLPQ(6x6)
包装: 标准包装
产品目录页面: 1383 (CN2011-ZH PDF)
其它名称: IR3514MTRPBFDKR
IR3514
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
x
x
x
x
x
x
x
x
x
Dedicate at least one middle layer for a ground plane LGND.
Connect the ground tab under the control IC to LGND plane through a via.
Separate analog bus (EAOUTx, VDACx and IINx) from digital bus (CLKIN, PHSIN, and PHSOUT) to reduce
the noise coupling.
Place VCCL decoupling capacitor CVCCL as close as possible to VCCL and LGND pins.
Place the following critical components on the same layer as control IC and position them as close as
possible to the respective pins, ROSC, ROCSETx, RVDACx, CVDACx, and CSS/DELx. Avoid using any via
for the connection.
Place the compensation components on the same layer as control IC and position them as close as possible
to EAOUTx, FBx, VOUTx and VDRP1 pins. Avoid using any via for the connection.
Use Kelvin connections for the remote voltage sense signals, VOSNSx+ and VOSNSx-, and avoid crossing
over the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.
Avoid analog control bus signals, VDACx, IINx, and especially EAOUTx, crossing over the fast transition
nodes.
Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation
components.
Page 41 of 46
10/30/2007
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