参数资料
型号: IR3514MTRPBF
厂商: International Rectifier
文件页数: 24/46页
文件大小: 0K
描述: IC XPHASE3 CONTROL HYBRD 40-MLPQ
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 1
系列: XPhase3™
应用: 处理器
安装类型: 表面贴装
封装/外壳: 40-MLPQ
供应商设备封装: 40-MLPQ(6x6)
包装: 标准包装
产品目录页面: 1383 (CN2011-ZH PDF)
其它名称: IR3514MTRPBFDKR
on fast-mode I C. SVID commands from an AMD processor are communicated through SVID bus pins SVC and
IR3514
Serial VID Interface Protocol and VID-on-the-fly Transition
The IR3514 supports the AMD SVI bus protocol and the AMD Server and desktop SVI wire protocol which is based
2
SVD. The SVC pin of the IR3514 does not have an open drain output since AMD SVID protocol does not support
slave clock stretching.
The IR3514 transitions from a 2-bit Boot VID mode to SVI mode upon assertion of PWROK. The SMBus send byte
protocol is used by the IR3514 VID-on-the-fly transactions. The IR3514 will wait until it detects a start bit which is
defined as an SVD falling edge while SVC is high. A 7bit address code plus one write bit (low) should then follow
the start bit. This address code will be compared against an internal address table and the IR3514 will reply with an
acknowledge ACK bit if the address is one of the three stored addresses otherwise the ACK bit will not be sent out.
The SVD pin is pulled low by the IR3514 to generate the ACK bit. Table 6 has the list of addresses recognized by
the IR3514.
The processor should then transmit the 8-bit data word immediately following the ACK bit. Data bit 7 is the PSI_L
bit which is followed by the 7Bit AMD code. The IR3514 replies again with an ACK bit once the data is received. If
the received data is not a VID-OFF command, the IR3514 immediately changes the DAC analog outputs to the new
target. VDAC1 and VDAC2 then slew to the new VID voltages. See Figure 12a and 12b for a send byte examples.
Table 6 - SVI Send Byte Address Table
SVI Address [6:0] + Wr
110xx100b
110xx010b
110xx110b
Description
Set VID only on Output 1
Set VID only on Output 2
Set VID on both Output 1 and Output 2
Note: ‘x’ in the above Table 4 means the bit could be either ‘1’ or ‘0’.
Figure 12a Send Byte Example
Page 24 of 46
10/30/2007
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