参数资料
型号: IR3514MTRPBF
厂商: International Rectifier
文件页数: 14/46页
文件大小: 0K
描述: IC XPHASE3 CONTROL HYBRD 40-MLPQ
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 1
系列: XPhase3™
应用: 处理器
安装类型: 表面贴装
封装/外壳: 40-MLPQ
供应商设备封装: 40-MLPQ(6x6)
包装: 标准包装
产品目录页面: 1383 (CN2011-ZH PDF)
其它名称: IR3514MTRPBFDKR
IR3514
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC1
PWM Latch SET
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 6 Four Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is
set. This event starts the PWM ramp voltage charge cycle, turns off the low side driver, and turns on the high side
driver after a non-overlap blank time. When the PWM ramp voltage exceeds the error amplifier’s output voltage, the
PWM latch is reset. This turns off the high side driver and then turns on the low side driver after the non-overlap
blank time; it activates the ramp discharge clamp, which quickly discharges the internal PWM ramp capacitor to the
output voltage of share adjust amplifier in phase IC until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in
ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.
Figure 7 depicts PWM operating waveforms under various conditions.
Page 14 of 46
10/30/2007
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