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| 型号： | IR3514MTRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 17/46页 |
| 文件大小： | 0K |
| 描述： | IC XPHASE3 CONTROL HYBRD 40-MLPQ |
| 产品变化通告： | (EP) Parts Discontinuation 25/May/2012 |
| 标准包装： | 1 |
| 系列： | XPhase3™ |
| 应用： | 处理器 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-MLPQ |
| 供应商设备封装： | 40-MLPQ（6x6） |
| 包装： | 标准包装 |
| 产品目录页面： | 1383 (CN2011-ZH PDF) |
| 其它名称： | IR3514MTRPBFDKR |
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IR3514
IR3514 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3514 is shown in Figure 3. The following discussions are applicable to either output
plane unless otherwise specified.
VID Interface Configuration
The IR3514 Hybrid Control IC can operate in either SVI (Serial VID Interface) or PVI (Parallel VID Interface) mode.
The state of VID1 upon ENABLE assertion determines which mode the IR3514 will operate in; VID1=0V enables the
SVI Dual Plane Mode, conversely VID1=”1” selects PVI Single Plane Mode.
SVI mode has the ability to independently control both the VDD core and VDDNB auxiliary planes required by the
CPU. The IR3514 can also receive Power Savings commands through the SVI serial bus and communicate this
information to the IR3507 or other Phase ICs with PSI input capabilities.
When operated in PVI (Parallel VID Interface) mode, the IR3514 controls the VDD core plane through 6 Parallel VID
bits and the VDDNB auxiliary plane power stage goes to high impedance.
Serial VID Control (VID1= ”0” at ENABLE assertion)
The two Serial VID Interface (SVID) pins SVC and SVD are used to program the Boot VID voltage upon assertion of
ENABLE while PWROK is de-asserted. See Table 2 for the 2-bit Boot VID codes. Both VDAC1 and VDAC2
voltages will be programmed to the Boot VID code until PWROK is asserted. The Boot VID code is stored by the
IR3514 to be utilized again if PWROK is de-asserted.
Serial VID communication from the processor is enabled after the PWROK is asserted. Addresses and data are
serially transmitted in 8-bit words. The IR3514 has three fixed addresses to control VDAC1, VDAC2, or both
VDAC1 and VDAC2 (See Table 6 for addresses). The first data bit of the SVID data word represents the PSI bit
which is passed on to the phase ICs via the IR3514 PSI_L pin. PSI_L is pulled high by an internal 10K resistor to
VCCL when data bit 7 of an SVID command is high. The remaining data bits SVID[6:0] select the desired VDACx
regulation voltage as defined in Table 3. SVID[6:0] are the inputs to the Digital-to-Analog Converter (DAC) which
then provides an analog reference voltage to the transconductance type buffer amplifier. This VDACx buffer
provides a system reference on the VDACx pin. The VDACx voltage along with error amplifier and remote sense
differential amplifier input offsets are post-package trimmed to provide a 0.5% system set-point accuracy, as
measured in Figures 4A and 4B. VDACx slew rates are programmable by properly selecting external series RC
compensation networks located between the VDACx and the LGND pins. The VDACx source and sink currents are
derived off the external oscillator frequency setting resistor, R ROSC . The programmable slew rate enables the
IR3514 to smoothly change the regulated output voltage throughout VID transitions resulting in a power supply input
and output capacitor inrush currents, along with output voltage overshoot, to be well controlled.
The two Serial VID Interface (SVID) pins SVC and SVD can also program the VFIX VID voltage upon assertion of
ENABLE while PWROK is equal to VCCL. See Table 3 for the 2-bit VFIX VID codes. Both VDAC1 and VDAC2
voltages will be programmed to the VFIX code. The SVC and SVD pins require external pull-up biasing and should
not be floated.
Bits
7
6:0
Description
PSI_L:
= 0 means the processor is at an optimal load for the regulator(s) to enter power-saving mode.
= 1 means the processor is not at an optimal load for the regulator(s) to enter power-saving mode.
SVID[6:0] as defined in Table 4.
Table 1. Serial VID 8-Bit Data Field Encoding
Page 17 of 46
10/30/2007
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