参数资料
型号: IRF530
厂商: MOTOROLA INC
元件分类: JFETs
英文描述: 100V,14A TMOS Power Field Effect Transistor (N-Channel Enhancement Mode Silicon Gate)(100V,14A TMOS功率场效应管(N沟道增强型硅门))
中文描述: 14 A, 100 V, 0.14 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB
封装: CASE 221A-09, 3 PIN
文件页数: 2/8页
文件大小: 166K
代理商: IRF530
IRF530
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
100
112
Vdc
V/
°C
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
10
100
mAdc
Gate–Body Leakage Current
(VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
100
nAdc
ON CHARACTERISTICS(1)
Gate Threshold Voltage
Cpk
≥ 2.0(3)
(VDS = VGS, ID = 0.25 mA)
Threshold Temperature Coefficient (Negative)
VGS(th)
2.0
2.9
6.2
4.0
Vdc
mV/
°C
Static Drain–to–Source On–Resistance
Cpk
≥ 2.0(3)
(VGS = 10 Vdc, ID = 8.0 Adc)
RDS(on)
0.098
0.140
Ohms
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 14 Adc)
(VGS = 10 Vdc, ID = 8.0 Adc, TJ = 125°C)
VDS(on)
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 8.0 Adc)
gFS
4.0
7.4
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V
25 Vdc V
0 Vdc
Ciss
700
800
pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
200
500
Transfer Capacitance
f = 1.0 MHz)
Crss
65
150
SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time
(V
36 Vd
I
8 0 Ad
td(on)
9.0
30
ns
Rise Time
(VDS = 36 Vdc, ID = 8.0 Adc,
tr
47
75
Turn–Off Delay Time
( DS
, D
,
VGS = 10 Vdc, RG = 15 )
td(off)
33
40
Fall Time
tf
34
45
Gate Charge
(V
80 Vd
I
14 Ad
QT
26
40
nC
(VDS = 80 Vdc, ID = 14 Adc,
Q1
5.0
( DS
, D
,
VGS = 10 Vdc)
Q2
13
Q3
11
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 14 Adc, VGS = 0 Vdc)
(IS = 14 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD
0.92
0.80
1.5
Vdc
Reverse Recovery Time
(I
14 Ad
trr
103
nS
(IS = 14 Adc,
ta
78
( S
,
dIS/dt = 100 A/S)
tb
25
Reverse Recovery Stored Charge
QRR
0.46
mC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25
″ from package to center of die)
Ld
3.5
nH
Internal Source Inductance
(Measured from screw on tab to source bond pad)
Ls
7.5
(1) Pulse Test: Pulse Width
≤ 300 S, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Cpk +
Max limit – Typ
3
sigma
相关PDF资料
PDF描述
IRF533 N-CHANNEL ENHANCEMENT-MODE SILICON GATE TMOS POWER FIELD EFFECT TRANSISTOR
IRF531 N-CHANNEL ENHANCEMENT-MODE SILICON GATE TMOS POWER FIELD EFFECT TRANSISTOR
IRF532 N-CHANNEL ENHANCEMENT-MODE SILICON GATE TMOS POWER FIELD EFFECT TRANSISTOR
IRF540 100V,27A TMOS Power Field Effect Transistor (N-Channel Enhancement Mode Silicon Gate)(100V,27A TMOS功率场效应管(N沟道增强型硅门))
IRF620-009 5.2 A, 200 V, 0.8 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB
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