参数资料
型号: IS45VS16160D-8BLA2
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: DRAM
英文描述: 16M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封装: 13 X 8 MM, 0.80 MM PITCH, LEAD FREE, MS-207, BGA-54
文件页数: 17/61页
文件大小: 939K
代理商: IS45VS16160D-8BLA2
24
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
04/21/09
IS42VS83200D, IS42VS16160D
IS45VS83200D, IS45VS16160D
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific mode
ofoperationoftheSDRAM.Thisdefinitionincludesthe
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODEREGISTERDEFINITION.
ThemoderegisterisprogrammedviatheLOADMODE
REGISTERcommandandwillretainthestoredinformation
until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequentialorinterleaved),M4-M6
specifytheCASlatency,M7andM8specifytheoperating
mode,M9specifiestheWRITEburstmode,andM10,M11,
andM12arereservedforfutureuse.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiatingthesubsequentoperation.Violatingeitherofthese
requirementswillresultinunspecifiedoperation.
MODE REGISTER DEFINITION
Latency Mode
M6 M5 M4
CAS Latency
0
Reserved
0
1
Reserved
0
1
0
2
0
1
3
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Reserved
1. To ensure compatibility with future devices,
should program BA1, BA0, A12, A11, A10 = "0"
Write Burst Mode
M9
Mode
0
Programmed Burst Length
1
Single Location Access
Operating Mode
M8 M7
M6-M0
Mode
0
Defined
Standard Operation
— —
All Other States Reserved
Burst Type
M3
Type
0
Sequential
1
Interleaved
Burst Length
M2 M1 M0
M3=0
M3=1
0
1
0
1
2
0
1
0
4
0
1
8
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Full Page
Reserved
Address Bus (Ax)
Mode Register (Mx)
(1)
BA1 BA0 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
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