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| 型号： | IS45VS16160D-8BLA2 |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| 封装： | 13 X 8 MM, 0.80 MM PITCH, LEAD FREE, MS-207, BGA-54 |
| 文件页数： | 21/61页 |
| 文件大小： | 939K |
| 代理商： | IS45VS16160D-8BLA2 |
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
04/21/09
IS42VS83200D, IS42VS16160D
IS45VS83200D, IS45VS16160D
CLK
CKE
HIGH
COLUMN ADDRESS
AUTO PRECHARGE
NO PRECHARGE
CS
RAS
CAS
WE
A0-A9
A10
BA0, BA1
BANK ADDRESS
A11, A12
READ COMMAND
READS
READ bursts are initiated with a READ command, as
shownintheREADCOMMANDdiagram.
Thestartingcolumnandbankaddressesareprovidedwith
theREADcommand,andautoprechargeiseitherenabledor
disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theburst.ForthegenericREADcommandsusedinthefol-
lowing illustrations, auto precharge is disabled.
DuringREADbursts,thevaliddata-outelementfromthe
starting column address will be available following the
CASlatencyaftertheREADcommand.Eachsubsequent
data-outelementwillbevalidbythenextpositiveclock
edge.The CAS Latency diagram shows general timing
for each possible CAS latency setting.
Uponcompletionofaburst,assumingnoothercommands
havebeeninitiated,theDQswillgoHigh-Z.Afull-pageburst
will continue until terminated. (At the end of the page, it will
wraptocolumn0andcontinue.)
DatafromanyREADburstmaybetruncatedwithasub-
sequentREADcommand,anddatafromafixed-length
READburstmaybeimmediatelyfollowedbydatafroma
READcommand.Ineithercase,acontinuousflowofdata
canbemaintained.Thefirstdataelementfromthenew
burst follows either the last element of a completed burst
or the last desired data element of a longer burst which
is being truncated.
ThenewREADcommandshouldbeissuedx cycles before
the clock edge at which the last desired data element is
valid, where x equalstheCASlatencyminusone.Thisis
showninConsecutiveREADBurstsforCASlatenciesof
twoandthree;dataelementn +3iseitherthelastofa
burstoffourorthelastdesiredofalongerburst.The256Mb
SDRAMusesapipelinedarchitectureandthereforedoes
notrequirethe2n rule associated with a prefetch architec-
ture.AREADcommandcanbeinitiatedonanyclockcycle
followingapreviousREADcommand.Full-speedrandom
read accesses can be performed to the same bank, as
showninRandomREADAccesses,oreachsubsequent
READmaybeperformedtoadifferentbank.
DatafromanyREADburstmaybetruncatedwithasub-
sequent WRITE command, and data from a fixed-length
READburstmaybeimmediatelyfollowedbydatafroma
WRITEcommand(subjecttobusturnaroundlimitations).
TheWRITEburstmaybeinitiatedontheclockedgeim-
mediatelyfollowingthelast(orlastdesired)dataelement
fromtheREADburst,providedthatI/Ocontentioncanbe
avoided. In a given system design, there may be a pos-
sibilitythatthedevicedrivingtheinputdatawillgoLow-Z
beforetheSDRAMDQsgoHigh-Z.Inthiscase,atleast
a single-cycle delay should occur between the last read
dataandtheWRITEcommand.
TheDQMinputisusedtoavoidI/Ocontention,asshown
inFiguresRW1andRW2.TheDQMsignalmustbeas-
serted(HIGH)atleastthreeclockspriortotheWRITE
command(DQMlatencyistwoclocksforoutputbuffers)
tosuppressdata-outfromtheREAD.OncetheWRITE
commandisregistered,theDQswillgoHigh-Z(orremain
High-Z),regardlessofthestateoftheDQMsignal,provided
theDQMwasactiveontheclockjustpriortotheWRITE
commandthattruncatedtheREADcommand.Ifnot,the
secondWRITEwillbeaninvalidWRITE.Forexample,if
DQMwasLOWduringT4inFigureRW2,thentheWRITEs
atT5andT7wouldbevalid,whiletheWRITEatT6would
be invalid.
TheDQMsignalmustbede-assertedpriortotheWRITE
command(DQMlatencyiszeroclocksforinputbuffers)
to ensure that the written data is not masked.
Afixed-lengthREADburstmaybefollowedby,ortruncated
with, a PRECHARGE command to the same bank (provided
thatautoprechargewasnotactivated), and a full-page burst
maybetruncatedwithaPRECHARGEcommandtothe
samebank.ThePRECHARGEcommandshouldbeissued
x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency
minusone.ThisisshownintheREADtoPRECHARGE
Note:A9is"Don'tCare"forx16.
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相关代理商/技术参数 |
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| IS46DR16128-3DBLA1 | 功能描述:动态随机存取存储器 Automotive 2G,1.8V DDR2,128Mx16,333Mhz RoHS:否 制造商:ISSI 数据总线宽度:16 bit 组织:1 M x 16 封装 / 箱体:SOJ-42 存储容量:16 MB 最大时钟频率: 访问时间:50 ns 电源电压-最大:7 V 电源电压-最小:- 1 V 最大工作电流:90 mA 最大工作温度:+ 85 C 封装:Tube |
| IS46DR16128-3DBLA1-TR | 功能描述:动态随机存取存储器 Automotive,2G,1.8V DDR2,128Mx16,333Mhz RoHS:否 制造商:ISSI 数据总线宽度:16 bit 组织:1 M x 16 封装 / 箱体:SOJ-42 存储容量:16 MB 最大时钟频率: 访问时间:50 ns 电源电压-最大:7 V 电源电压-最小:- 1 V 最大工作电流:90 mA 最大工作温度:+ 85 C 封装:Tube |
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