参数资料
型号: IS61DDB22M18
厂商: Integrated Silicon Solution, Inc.
英文描述: 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
中文描述: 36字节(100万× 36
文件页数: 18/25页
文件大小: 421K
代理商: IS61DDB22M18
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
2/22/05
ISSI
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and
printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM
core.
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST
signal is not required.
Signal List
TCK: test clock
TMS: test mode select
TDI: test data-in
TDO: test data-out
JTAG DC Operating Characteristics
(T
A
= 0 to +
70°
C)
Operates with JEDEC Standard 8-5 (1.8V) logic signal levels
Parameter
Symbol
Minimum
Typical
Maximum
Units
Notes
JTAG input high voltage
V
IH1
1.3
V
DD
+0.3
V
1
JTAG input low voltage
V
IL1
-0.3
0.5
V
1
JTAG output high level
V
OH1
V
DD
-0.4
V
DD
V
1, 2
JTAG output low level
V
OL1
V
SS
0.4
V
1, 3
1. All JTAG inputs and outputs are LVTTL-compatible.
2. I
OH1
-|2mA|
3. I
OL1
+|2mA|.
JTAG AC Test Conditions
(T
A
= 0 to +
70°
C, V
DD
= 1.8V -5%, +5%)
Parameter
Symbol
Conditions
Units
Input pulse high level
V
IH1
1.3
V
Input pulse low level
V
IL1
0.5
V
Input rise time
T
R1
1.0
ns
Input fall time
T
F1
1.0
ns
Input and output timing reference level
0.9
V
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