参数资料
型号: IS61DDB22M18
厂商: Integrated Silicon Solution, Inc.
英文描述: 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
中文描述: 36字节(100万× 36
文件页数: 8/25页
文件大小: 421K
代理商: IS61DDB22M18
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
2/22/05
ISSI
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
Timing Reference Diagram for Truth Table
Clock Truth Table
(Use the following table with the
Timing Reference Diagram for Truth Table
.)
Mode
Clock
Controls
Data-Out/Data-In
K
LD
R/W
Q
A
/ D
B
Q
A+1
/ D
B+1
Stop Clock
Stop
X
X
Previous state
Previous state
No Operation (NOP)
L
H
H
H
High-Z
High-Z
Read A
L
H
L
X
D out at C (t + 1.5)
D out at C (t + 2)
Write B
L
H
X
L
D
B
(t
W
+ 1)
D
B
(t
W
+ 1.5)
Notes
:
1. The internal burst counter is always fixed as two-bit.
2. X = don’t care; H = logic “1”; L = logic “0”.
3. A read operation is started when control signal R/W is active high.
4. A write operation is started when control signal R/W is active low.
5. Before entering into the stop clock, all pending read and write commands must be completed.
6. For timing definitions, refer to the
AC Characteristics
on page
15
. Signals must have AC specifications at timings indicated in
parenthesis with respect to switching clocks K, K, C, and C.
t
t+1
t+2
t
w
Write B
NOP
A
QA
QA+1
K Clock
K Clock
LD
R / W
BW 0,1,2,3
Address
Data-In/
C Clock
C Clock
CQ Clock
CQ Clock
Cycle
t
w+1
DB
DB+1
NOP
Read A
B
Data-Out (DQ)
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IS61DDB22M36 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs