参数资料
型号: ISL35822IK
厂商: Intersil
文件页数: 28/75页
文件大小: 0K
描述: IC CLOCK/DATA RECOVERY 192EBGA-B
标准包装: 90
类型: 时钟和数据恢复(CDR),多路复用器
PLL:
输入: CML
输出: CML,CMOS
电路数: 1
比率 - 输入:输出: 8:8
差分 - 输入:输出: 是/是
频率 - 最大: 3.1875Gbps
电源电压: 1.425 V ~ 1.575 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 192-EBGA
供应商设备封装: 192-EBGA-B(17x17)
包装: 托盘
34
Note (1): Loopback is from Serial I/P to Serial O/P. Recommended use for test purposes only; the lanes are swapped, and no pre-emphasis is performed.
Note (2): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): Default values depend on setting of LX4/CX4 select LX4_MODE pin. LX4 value is shown firs
t. The values may be overwritten by the Auto-Configure operation
Note (1): See Figure 3 for illustration of the pre-emphasized waveform and meaning of symbols.
Note (2): This equation is the one used by the IEEE 802.3 CX4 Working Group when discussing pre-emphasis (alias Transmit equalization). The template normalization
factor of 0.69 in step 6) of IEEE 802.3akD5.3 Section 54.6.3.6 reflects 0.31 (31%) pre-emphasis according to this equation.
Note (3): This is the Default value set on power-up or RESET if the LX4/CX4 LX4_MODE pin is set for LX4 operation. This setting allows for a lowered device power
consumption by using the Lowered Power bits to turn off the pre-emphasis drivers (seeTable 45
).
Note (4): This is the Default value set on power-up or RESET if the LX4/CX4 LX4_MODE pin is set for CX4 operation. This setting allows for a small loss in the PCB
traces and connectors before the IEEE 802.3akD5.3 defined TP2 compliance measurement point. The value may be overwritten by the Auto-Configure
Table 40. PMA SERIAL LOOP BACK CONTROL REGISTER
MDIO REGISTER ADDRESS = 1.49156 (1.C004’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.49156.15:13
Reserved
1.49156.12
PMA Test LP
1 = enable
0 = disable
0’h(1)
R/W
Serial Network Test Loopback
1.49156.11
PMA SLP_3
0’b(2)
R/W
PMA Serial Loop Back Enable for each individual
lane. When high, it routes the internal PMA Serial
output to the PMA Serial input.
1.49156.10
PMA SLP_2
0’b(2)
1.49156.9
PMA SLP_1
0’b(2)
1.49156.8
PMA SLP_0
0’b(2)
1.49156.7:0
Reserved
Table 41. PMA PRE-EMPHASIS CONTROL
MDIO REGISTER ADDRESS = 1.49157 (1.C005’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
1.49157.15:12
PRE_EMP Lane 3
See Table 42 for
settings
00’h/07’h
R/W
Configure the level of PMA pre-emphasis
(if Enabled, see 1.C01B.5:2 in Table 45)
1.49157.11:8
PRE_EMP Lane 2
00’h/07’h
R/W
1.49157.7:4
PRE_EMP Lane 1
00’h/07’h
R/W
1.49157.3:0
PRE_EMP Lane 0
00’h/07’h
R/W
Table 42. PMA PRE-EMPHASIS CONTROL SETTINGS
(1)
ADDRESS
1.C005’h
BITS 3:0
PRE-EMPHASIS
(802.3ak) (2) =
(1-VLOW/VHI)
PRE-EMPHASIS
VALUE =
(VHI/ VLOW)-1
ADDRESS
1.C005’h
BITS 3:0
PRE-EMPHASIS
(802.3ak) (2) =
(1-VLOW/VHI)
PRE-EMPHASIS
VALUE =
(VHI/ VLOW)-1
0000(3)
0%
0
1000
33.0%
0.493
0001
5.0%
0.053
1001
36.5%
0.575
0010
9.5%
0.105
1010
40.0%
0.667
0011
14.0%
0.163
1011
43.0%
0.754
0100
18.5%
0.227
1100
46.0%
0.852
0101
22.0%
0.282
1101
49.0%
0.961
0110
26.5%
0.361
1110
52.0%
1.083
0111(4)
30.0%
0.429
1111
54.5%
1.198
ISL35822
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