参数资料
| 型号： | ISL35822IK |
| 厂商： | Intersil |
| 文件页数： | 68/75页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 192EBGA-B |
| 标准包装： | 90 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 无 |
| 输入： | CML |
| 输出： | CML，CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 8:8 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 3.1875Gbps |
| 电源电压： | 1.425 V ~ 1.575 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 192-EBGA |
| 供应商设备封装： | 192-EBGA-B（17x17） |
| 包装： | 托盘 |
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70
FIGURE 24. I2C OPERATION TIMING
Applications Information
CX4/LX4/XAUI Re-timer Setup
This section discusses the setup for the ISL35822 to be
used as a XAUI/CX4/LX4 Retimer. The various descriptions
and comments further assume that the device is initially
configured in the default condition (i.e. exactly as found after
a hardware reset). The BIST_ENA pin should be pulled
LOW (to GND); the pin has an internal pulldown to this
value. The LX4_MODE select pin should be tied to the
appropriate level, depending on whether the ISL35822 is
interfaced to a CX4 connection, or a XAUI/LX4 interface
(where it is assumed that the electro-optical interface is
XAUI-compatible).
Although the ISL35822 will come out of reset with CX4 or
LX4-directed values, some of these default register settings
may need to be changed, for optimum operation in any
specific application. All of these may be set via the Auto-
Configure operation (See “Auto-Configuring Control
The default values of pre-emphasis and receive equalization
set by the LX4_MODE select pin may need to be adjusted,
particularly if the serial 3Gbps PCB traces on the ‘host’ side
(the XAUI or the XENPAK/XPAK/X2 side) are long, (in which
case the PHY XS values may need adjustment), or if the
connection to a CX4 connector or laser driver and photo
detector and limiting amplifier involve extra connectors, long
traces, or enhanced edge rates (in which case the PMA/D
values should be adjusted). Note that in LX4 mode, the
PMA-side pre-emphasis will have to be enabled, and the
power consumption of the device will be increased.
The default value of the PMA/D and PHY XS XAUI_EN bits
is set at ‘1’, and for normal XAUI or CX4/LX4 operation, this
is usually the best setting for this use. Byte alignment will
follow the IEEE 802.3ae PCS SYNC specification, Lane
alignment will follow the DESKEW algorithm in the same
specification, and the pseudo-random /A/K/R/ generation in
IDLE will also be performed according to the same
specifications.
For certain non-10GBASE-X uses, or for debug and problem
analysis purposes, and in particular for certain BIST testing,
it may be advantageous to change some of the settings. To
achieve this, the relevant (PMA/D and/or PHY XS) XAUI_EN
bits must be turned off (to ‘0’), since otherwise they will
override many of the other registers’ bits (see Table 65). For
instance, if it desirable to change Byte Alignment to a
simpler algorithm than the IEEE-defined one (if, for example,
only three of the four lanes are working), the
turned off, and (with the respective XAUI_EN bit off), byte
(code group) alignment on the working lanes will now
function. Similarly, setting the A_ALIGN_DIS bit in the
PCS/PHY XS Control Register 2 ([3,4].C000’h) will cause
lane alignment to occur on IDLE to non-IDLE transitions
across all four lanes, instead of lane alignment on ||A||
(K28.3) character columns when this bit is set to a zero. The
internal (pseudo-XGMII) ERROR character can be set to a
value other than 1FE’h by writing the value (without the K bit)
to register 3.C002’h or 4.C002’h. Similarly, the internal
(pseudo-XGMII) IDLE character may be changed using
registers 3.C003’h and/or 4.C003’h. The pseudo-random
XAUI/CX4/LX4 IDLE /A/K/R/ generator can be disabled by
clearing the AKR_SM_EN bit in register 3.C001’h (PCS) or
4.C001’h (PHY XS). To disallow complete regeneration of
the Inter Packet Gap (IPG), it would be desirable to clear the
TRANS_EN bit in register 3.C001’h/4.C001’h.
Recommended Analog Power and Ground Plane
Splits
The ISL35822 high-speed analog circuits as well as high-
speed I/O draw power from the analog power (VDDA) and
(shared) ground GNDA pins/balls (pins or balls will be used
inter-changeably through out this document). In order for the
ISL35822 to achieve best performance, the VDDA and
Data
Stop
Data
Start
SCL
SDA
T
SCLH_L
T
SCL_DAV
T
SDA_CLV
T
SDA_CLV
ISL35822
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL35822LP | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Octal 2.488Gbps to 3.187Gbps/ Lane Retimer |
| ISL35822LPIK | 功能描述:IC CLOCK/DATA RECOVERY 192EBGA-B RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ISL36111 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:11.1Gb/s Lane Extender |
| ISL36111DRZ-EVALZ | 功能描述:EVAL BOARD FOR ISL36111DRZ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:* 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 主要目的:电源管理，电池充电器 嵌入式:否 已用 IC / 零件:MAX8903A 主要属性:1 芯锂离子电池 次要属性:状态 LED 已供物品:板 |
| ISL36111DRZ-T7 | 功能描述:IC EQUALIZER REC 11.1GBPS 16QFN RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:QLx™ 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
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