参数资料
| 型号： | ISL35822IK |
| 厂商： | Intersil |
| 文件页数： | 43/75页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 192EBGA-B |
| 标准包装： | 90 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 无 |
| 输入： | CML |
| 输出： | CML，CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 8:8 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 3.1875Gbps |
| 电源电压： | 1.425 V ~ 1.575 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 192-EBGA |
| 供应商设备封装： | 192-EBGA-B（17x17） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页当前第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页
48
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (3): These state machines are implemented according to 802.3ae-2002 clause 48.
Note (4): If the RCLKMODE bits are set to 10’b, the internal XGMII clock from the PHY XS to the PCS is set to the recovered clock. If the PHY XS Clock PSYNC bit is set (the
default), the recovered clock from Lane 0 is used for all four lanes, if cleared, or if the RCLKMODE bits are set to 01’b or 00’b, each lane uses its own recovered clock.
If the incoming data is NOT frequency-synchronous with the local reference clock, data will be corrupted (occasional characters will be lost, or repeated).
Note (5): This bit name reflects the “embedded” PCS function within an XGXS, see IEEE 802.3 Clause 47.2.1.
4.49152.4
PHY XS
PCS_SYNC_EN(5)
0 = disable(2)
1 = enable
0’b
R/W
Enable 8b/10b PCS coding synchronized state machine(3) to
control the byte alignment (IEEE ‘code-group alignment’) of
the high speed de-serializer
4.49152.3
PHY XS IDLE_D_EN
1 = enable
0 = disable
1’b
R/W
Enables IDLE vs. NON-IDLE detection for lane alignment.
Overridden by PHY XS XAUI_EN, see Table 88
4.49152.2
PHY XS ELST_EN
1 = enable
0 = disable
1’b
R/W
Enable the elastic function of the PHY XS receiver buffer
4.49152.1
PHY XS
A_ALIGN_DIS
1 = disable(2)
0 = enable
1’b
R/W
PHY XS Receiver aligns data on incoming “/A/” characters
(K28.3). If disabled (default), receiver aligns data on IDLE to
non-IDLE transitions (if bit 3 set). Overridden by PHY XS
XAUI_EN, see Table 81
4.49152.0
PHY XS CAL_EN
1 = enable
0 = disable
1’b
R/W
Enable de-skew calculator of PHY XS receiver Align FIFO
Table 80. PHY XS CONTROL REGISTER 2 (Continued)
MDIO REGISTER ADDRESS = 4.49152 (4.C000’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
Table 81. PHY XS CONTROL REGISTER 3
MDIO REGISTER ADDRESS = 4.49153 (4.C001’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
4.49153.15
PHY XS DC_O_DIS 1 = Disable, 0 = normal
0’b
R/W
PHY XS DC Offset Disable
4.49153.14:13
Reserved
4.49153.12
MF_SEL
Select source of signals
for four MF pins
0’b
R/W
1 = Select signals from PMA/PCS
to be output on MF pins
0 = Select signals from PHY
XGXS to be output on MF pins
4.49153.11
PHY XS XAUI_EN
1 = enable
0 = disable
1’b
R/W
Enables all XAUI features per 802.3ae-2002. It is
equivalent to setting the configuration bits listed in
Table 65 (but does not change the actual value of the
corresponding MDIO registers’ bits).
4.49153.10:8
PHY_LOS_TH
0’h = 160mVp-p
1’h = 240mVp-p
2’h = 200mVp-p
3’h = 120mVp-p
4’h = 80mVp-p
else = 160mVp-p
000’b
R/W
Set the threshold voltage for the Loss Of Signal
(LOS) detection circuit in PHY XS. Nominal levels are
listed for each control value. Note that the differential
peak-to-peak value is twice that listed
4.49153.7
Reserved
4.49153.6
PHY XS
AKR_SM_EN
1 = enable random A/K/R
0 = /K/ only(2)
0’b
R/W
Enable pseudo- random A/K/R(3) in Inter Packet Gap
(IPG) on transmitter side (vs. /K/ only)
4.49153.5
PHY XS TRANS_EN 1 = enable
0 = disable(2)
Overridden by PHY XS
XAUI_EN, see Table 65
0’b
R/W
This bit enables the transceiver to translate an “IDLE”
pattern in the internal FIFOs (matching the value of
register 4.C003’h) to and from the XAUI IDLE /K/
comma character or /A/, /K/ & /R/ characters.
4.49153.4
Reserved
4.49153.3
PHY XS TX_SDR
PHY XS receive
data rate
0’b
R/W
1 = PHY XS takes data from PCS at half speed
0 = PHY XS takes data from PCS at full speed
ISL35822
相关PDF资料 |
PDF描述 |
|---|---|
| VI-22Y-MX-S | CONVERTER MOD DC/DC 3.3V 49.5W |
| VI-22Y-MW-S | CONVERTER MOD DC/DC 3.3V 66W |
| MS27474E16B55PA | CONN RCPT 55POS JAM NUT W/PINS |
| V24A24M300BF3 | CONVERTER MOD DC/DC 24V 300W |
| D38999/24KC4SA | CONN RCPT 4POS JAM NUT W/SCKT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL35822LP | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Octal 2.488Gbps to 3.187Gbps/ Lane Retimer |
| ISL35822LPIK | 功能描述:IC CLOCK/DATA RECOVERY 192EBGA-B RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ISL36111 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:11.1Gb/s Lane Extender |
| ISL36111DRZ-EVALZ | 功能描述:EVAL BOARD FOR ISL36111DRZ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:* 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 主要目的:电源管理，电池充电器 嵌入式:否 已用 IC / 零件:MAX8903A 主要属性:1 芯锂离子电池 次要属性:状态 LED 已供物品:板 |
| ISL36111DRZ-T7 | 功能描述:IC EQUALIZER REC 11.1GBPS 16QFN RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:QLx™ 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
发布紧急采购，3分钟左右您将得到回复。