参数资料
型号: ISL6308ACRZ
厂商: Intersil
文件页数: 11/28页
文件大小: 0K
描述: IC CTRLR PWM BUCK 3PHASE 40-QFN
标准包装: 500
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6308A
MOSFET driver detects the change in state of the PWM
signal and turns off the synchronous MOSFET and turns on
the upper MOSFET. The PWM signal will remain high until
the pulse termination signal marks the beginning of the next
cycle by triggering the PWM signal low.
Channel Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, I n ,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, I AVG , provides a measure of the total load
current demand on the converter during each switching
cycle. Channel current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
uses the ISEN inputs to reproduce a signal proportional to
the inductor current, I L . This sensed current, I SEN , is simply
a scaled version of the inductor current. The sample window
opens exactly 1/6 of the switching period, t SW , after the
PWM transitions low. The sample window then stays open
the rest of the switching cycle until PWM transitions high
again, as illustrated in Figure 4.
The sampled current, at the end of the t SAMPLE , is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used only
for channel current balance.
I L
PWM
SWITCHING PERIOD
I SEN
SAMPLING PERIOD
pulse width based on the error. Intersil’s patented current-
balance method is illustrated in Figure 3, with error
OLD SAMPLE
CURRENT
NEW SAMPLE
CURRENT
correction for channel 1 represented. In the figure, the cycle
average current, I AVG , is compared with the Channel 1
sample, I 1 , to create an error signal I ER .
The filtered error signal modifies the pulse width
commanded by V COMP to correct any unbalance and force
I ER toward zero. The same method for error signal
correction is applied to each active channel.
TIME
FIGURE 4. SAMPLE AND HOLD TIMING
The ISL6308A supports MOSFET r DS(ON) current sensing
to sample each channel’s current for channel current
balance. The internal circuitry, shown in Figure 5 represents
Channel N of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
V COMP
+
-
+
-
PWM1
TO GATE
CONTROL
LOGIC
active depending on the status of the PVCC3 and PVCC2
pins, as described in “PWM Operation” on page 10.
V IN
f(s)
FILTER
Σ
I SEN = I x -------------------------- )
DS ( ON
R ISEN
SAWTOOTH SIGNAL
I ER
I AVG
÷ N
-
+
I 1
NOTE: Channel 2 and 3 are optional.
I 3
I 2
I n
SAMPLE
AND
HOLD
L
r
-
+
ISEN(n)
R ISEN
CHANNEL N
UPPER MOSFET
I L
-
I L x r DS ( ON )
+
FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
CHANNEL N
LOWER MOSFET
Current Sampling
ISL6308A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
In order to realize proper current balance, the currents in
each channel must be sampled every switching cycle. This
sampling occurs during the forced off-time, following a PWM
transition low. During this time the current sense amplifier
11
FIGURE 5. ISL6308A INTERNAL AND EXTERNAL CURRENT-
SENSING CIRCUITRY FOR CURRENT BALANCE
FN6669.0
September 9, 2008
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