参数资料
| 型号： | ISL6308ACRZ |
| 厂商： | Intersil |
| 文件页数： | 12/28页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 3PHASE 40-QFN |
| 标准包装： | 500 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页当前第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
ISL6308A
The ISL6308A senses the channel load current by sampling
TABLE 1. ISL6308A DAC VOLTAGE SELECTION TABLE
the voltage across the lower MOSFET r DS(ON) , as shown in
Figure 5. A ground-referenced operational amplifier, internal
to the ISL6308A, is connected to the PHASE node through a
resistor, R ISEN . The voltage across R ISEN is equivalent to
the voltage drop across the r DS(ON) of the lower MOSFET
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, I L . The ISEN current is
REF1
0
0
1
1
REF0
0
1
0
1
VDAC
0.600V
0.900V
1.200V
1.500V
I n = I L ? ----------------------
derived where I L is the channel current.
r DS ( ON )
(EQ. 3)
R ISEN
Output Voltage Setting
The ISL6308A uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
the REF1, REF0 pins. The DAC decodes the 2-bit logic
signals into one of the discrete voltages shown in Table 1.
Each REF0 and REF1 pins are pulled up to an internal 1.2V
voltage by weak current sources (40μA current, decreasing
to 0 as the voltage at the REF0, REF1 pins varies from 0 to
the internal 1.2V pull-up voltage). External pull-up resistors
or active-high output stages can augment the pull-up current
sources, up to a voltage of 5V. The DAC pin must be
connected to REF pin through a 1k Ω to 5k Ω resistor and a
filter capacitor (0.022μF) is connected between REF and
GND.
The ISL6308A accommodates the use of external voltage
reference connected to REF pin if a different output voltage
is required. The DAC voltage must be set at least as high as
the external reference. The error amp internal noninverting
input is the lower of REF or (DAC +300mV).
A third method for setting the output voltage is to use a
resistor divider (R P1 , R S1 ) from the output terminal (V OUT )
to VSEN pin to set the output voltage level as shown in
Figure 6. This method is good for generating voltages up to
2.3V (with the REF voltage set to 1.5V).
Voltage Regulation
In order to regulate the output voltage to a specified level, the
ISL6308A uses the integrating compensation network shown in
Figure 6. This compensation network insures that the steady
state error in the output voltage is limited only to the error in the
reference voltage (output of the DAC or the external voltage
reference) and offset errors in the OFS current source, remote
sense and error amplifiers. Intersil specifies the guaranteed
tolerance of the ISL6308A to include the combined tolerances
of each of these elements, except when an external reference
or voltage divider is used, then the tolerances of these
components has to be taken into account.
The ISL6308A incorporates an internal differential remote-
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the controller ground reference point,
resulting in a more accurate means of sensing output voltage.
Connect the microprocessor sense pins to the non-inverting
input, VSEN, and inverting input, RGND, of the remote-sense
amplifier. The droop voltage, VDROOP, also feeds into the
remote-sense amplifier. The remote-sense output, VDIFF, is
therefore equal to the sum of the output voltage, VOUT, and
the droop voltage. VDIFF is connected to the inverting input of
the error amplifier through an external resistor.
The output of the error amplifier, V COMP , is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers and
regulate the converter output so that the voltage at FB is equal
to the voltage at REF. This will regulate the output voltage to
be equal to Equation 5. The internal and external circuitry that
---------------------------------- ? + V OFS – V DROOP
( R S1 + R P1 ) (EQ. 4)
For this case, the output voltage can be obtained as follows:
OUT = V REF ? R
P1
It is recommended to choose resistor values of less than
500 Ω for R S1 and R P1 resistors in order to get better output
voltage DC accuracy.
controls voltage regulation is illustrated in Figure 6.
V OUT = V REF ± V OFST – V DROOP
(EQ. 5)
12
FN6669.0
September 9, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6308ACRZR5609 | 制造商:Intersil Corporation 功能描述:PB-FREE DAC-LESS MULTI-PHASE PWM CONTR W/3-DRIVERS, HARD WI - Rail/Tube |
| ISL6308ACRZ-T | 功能描述:IC CTRLR PWM BUCK 3PHASE 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6308ACRZ-TR5609 | 制造商:Intersil Corporation 功能描述:PB-FREE DAC-LESS MULTI-PHASE PWM CONTR W/3-DRIVERS, HARD WIR - Tape and Reel |
| ISL6308AEVAL1Z | 功能描述:EVALUATION BOARD FOR ISL6308A RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6308AIRZ | 功能描述:IC CTRLR PWM BUCK 3PHASE 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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