参数资料
型号: ISL6308ACRZ
厂商: Intersil
文件页数: 19/28页
文件大小: 0K
描述: IC CTRLR PWM BUCK 3PHASE 40-QFN
标准包装: 500
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6308A
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 17, the
average driver current can be estimated with Equations 20
and 21, respectively.
P UP , 2 ≈ V IN ? ? ------ – --------- ? ? ? ---- 2 ? ? F SW
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
approximate power loss is P UP,2 .
? I M I PP ? ? t ?
? N 2 ? ? 2 ?
(EQ. 17)
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
3
2
(EQ. 20)
A third component involves the lower MOSFET
reverse-recovery charge, Q rr . Since the inductor current has
fully commutated to the upper MOSFET before the
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
I DR = ? --- ? Q G1 ? N
lower-MOSFET body diode can recover all of Q rr , it is
conducted through the upper MOSFET across V IN . The
power dissipated as a result is P UP,3 .
3
? 2
Q1
?
+ Q G2 ? N Q2 ? ? N PHASE ? F SW + I Q
(EQ. 21)
P UP , 3 = V IN ? Q rr ? F SW
(EQ. 18)
In Equations 20 and 21, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power
Finally, the resistive part of the upper MOSFET is given in
Equation 19 as P UP,4 .
loss; the gate charge (Q G1 and Q G2 ) is defined at the
particular gate to source drive voltage PVCC in the
I PP2
? I M ?
P UP , 4 ≈ r DS ( ON ) ? d ? ? ------ ? + ----------
? N ? 12
2
(EQ. 19)
corresponding MOSFET data sheet; I Q is the driver total
quiescent current with no load at both drive outputs; N Q1
and N Q2 are the number of upper and lower MOSFETs per
phase, respectively; N PHASE is the number of active
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 16, 17, 18 and 19. Since the power
equations depend on MOSFET parameters, choosing the
phases. The I Q* VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
300kHz.
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
PVCC
BOOT
C GD
D
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
R HI1
R LO1
UGATE
G
R G1
R GI1
C GS
C DS
Q1
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 6x6 QFN package is approximately 4W at
S
PHASE
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
C GD
room temperature. See “Layout Considerations” on page 25
for thermal transfer improvement suggestions.
R HI2
LGATE
G
C DS
When designing the ISL6308A into an application, it is
recommended that the following calculation is used to
R LO2
R G2
R GI2
C GS
Q2
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P Qg_TOT , due to the gate charge of MOSFETs and the
integrated driver ’s internal circuitry and their corresponding
19
S
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FN6669.0
September 9, 2008
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