参数资料
| 型号： | ISL6308ACRZ |
| 厂商： | Intersil |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 3PHASE 40-QFN |
| 标准包装： | 500 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 管件 |
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ISL6308A
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from Equation 11:
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6308A is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6308A will not inadvertently turn off unless the
C BOOT_CAP ≥ --------------------------------------
Q GATE
Δ V BOOT_CAP
(EQ. 11)
bias voltage drops substantially (see “Electrical
Specifications” table on page 5).
Q GATE = --------------------------------- ? N Q1
Q G1 ? PVCC
V GS1
ISL6308A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
where Q G1 is the amount of gate charge per upper MOSFET
at V GS1 gate-source voltage and N Q1 is the number of
control MOSFETs. The Δ V BOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive. Figure 10
shows the boot capacitor ripple voltage as a function of boot
capacitor value and total upper MOSFET gate charge.
1.6
1.4
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
PVCC1
+ 12 V
10.7k Ω
ENLL
1.40k Ω
1.2
1.0
0.8
0.6
0.4
Q GATE = 100nC
50nC
0.66V
SOFT-START
AND
FAULT LOGIC
FIGURE 11. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (ENLL) FUNCTION
0.2
20nC
2. The voltage on ENLL must be above 0.66V. The EN input
allows for power sequencing between the controller bias
0.0
0.0
0.1
0.2
0.3
0.4 0.5 0.6
Δ V BOOT_CAP (V)
0.7
0.8
0.9
1.0
voltage and another voltage rail. The enable comparator
holds the ISL6308A in shutdown until the voltage at ENLL
rises above 0.66V. The enable comparator has 100mV of
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6308A provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the
ENLL, VCC, PVCC and the REF0 and REF1 pins. When the
conditions are met, the controller begins soft-start. Once the
output voltage is within the proper window of operation, the
controller asserts PGOOD.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6308A
is released from shutdown mode.
15
hysteresis to prevent bounce.
3. The driver bias voltage applied at the PVCC pins must
reach the internal power-on reset (POR) rising threshold.
In order for the ISL6308A to begin operation, PVCC1 is
the only pin that is required to have a voltage applied that
exceeds POR. However, for 2 or 3-phase operation
PVCC2 and PVCC3 must also exceed the POR
threshold. Hysteresis between the rising and falling
thresholds assure that once enabled, the ISL6308A will
not inadvertently turn off unless the PVCC bias voltage
drops substantially (see “Electrical Specifications” table
on page 5).
When each of these conditions is true, the controller
immediately begins the soft-start sequence.
Soft-Start
During soft-start, the DAC voltage ramps linearly from zero
to the programmed level. The PWM signals remain in the
high-impedance state until the controller detects that the
ramping DAC level has reached the output-voltage level.
This protects the system against the large, negative inductor
currents that would otherwise occur when starting with a
pre-existing charge on the output as the controller attempted
FN6669.0
September 9, 2008
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相关代理商/技术参数 |
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| ISL6308ACRZR5609 | 制造商:Intersil Corporation 功能描述:PB-FREE DAC-LESS MULTI-PHASE PWM CONTR W/3-DRIVERS, HARD WI - Rail/Tube |
| ISL6308ACRZ-T | 功能描述:IC CTRLR PWM BUCK 3PHASE 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6308ACRZ-TR5609 | 制造商:Intersil Corporation 功能描述:PB-FREE DAC-LESS MULTI-PHASE PWM CONTR W/3-DRIVERS, HARD WIR - Tape and Reel |
| ISL6308AEVAL1Z | 功能描述:EVALUATION BOARD FOR ISL6308A RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6308AIRZ | 功能描述:IC CTRLR PWM BUCK 3PHASE 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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