参数资料
型号: ISL6308ACRZ
厂商: Intersil
文件页数: 22/28页
文件大小: 0K
描述: IC CTRLR PWM BUCK 3PHASE 40-QFN
标准包装: 500
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6308A
voltage) is compared with the oscillator (OSC) modified saw-
F 0 > ---------------------------------
R 2 = R 1 ? -----------------------------------------------
2 π ? V OSC ? R 1 ? F 0 ? L
Case 3:
1
2 π ? C ? ESR
2 π ? F 0 ? V OSC ? L
0.66 ? V IN ? ESR
0.66 ? V IN ? ESR ? C
C 2 = ---------------------------------------------------------------
tooth wave to provide a pulse-width modulated wave with an
amplitude of V IN at the PHASE node. The PWM wave is
smoothed by the output filter (L and C). The output filter
capacitor bank’s equivalent series resistance is represented by
the series resistor E.
C 2
In Equations 28, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent series
resistance of the bulk output filter capacitance; and V PP is
the peak-to-peak sawtooth signal amplitude, as described in
the “Electrical Specifications” table.
COMP
R 2
E/A
-
+
C 1
FB
R 3
R 1
C 3
Once selected, the compensation values in Equations 28
assure a stable converter with reasonable transient
VREF
VDIFF
performance. In most cases, transient performance can be
improved by making adjustments to R 2 . Slowly increase the
value of R 2 while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C 1 will not need adjustment. Keep the value of C 1 from
Equations 28 unless some performance issue is noted.
-
+
OSCILLATOR
RGND
VSEN
V OUT
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (see Figure 19). Keep
a position available for C 2 , and be prepared to install a high
frequency capacitor of between 22pF and 150pF in case any
PWM
CIRCUIT
V OSC
UGATE
V IN
L
DCR
leading edge jitter problem is noted.
Compensating the Converter Operating Without
Load-Line Regulation
The ISL6308A multi-phase converter operating without load
HALF-BRIDGE
DRIVE
PHASE
LGATE
C
ESR
line regulation behaves in a similar manner to a voltage-
mode controller. This section highlights the design
ISL6308A
EXTERNAL CIRCUIT
consideration for a voltage-mode controller requiring external
compensation. To address a broad range of applications, a
type-3 feedback network is recommended (see Figure 20).
C 2
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
R 2
C 1
COMP
function of V OUT /V COMP . This function is dominated by a DC
gain, given by d MAX V IN /V OSC , and shaped by the output
filter, with a double pole break frequency at F LC and a zero at
C 3
FB
F CE . For the purpose of this analysis, L and DCR represent
the individual channel inductance and its DCR divided by 3
R 3
R 1
VDIFF
ISL6308A
(equivalent parallel value of the three output inductors), while
C and ESR represents the total output capacitance and its
equivalent series resistance.
F LC = ---------------------------
F CE = ---------------------------------
FIGURE 20. COMPENSATION CONFIGURATION FOR
NON-LOAD-LINE REGULATED ISL6308A
1
2 π ? L ? C
1
2 π ? C ? ESR
(EQ. 29)
Figure 21 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable, with a
small number of adjustments, to the multi-phase ISL6308A
circuit. The output voltage (V OUT ) is regulated to the reference
voltage, VREF, level. The error amplifier output (COMP pin
22
The compensation network consists of the error amplifier
(internal to the ISL6308A) and the external R 1 -R 3 , C 1 -C 3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F 0 ; typically 0.1 to 0.3 of F SW ) and adequate phase
FN6669.0
September 9, 2008
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