参数资料
型号: ISL6308ACRZ
厂商: Intersil
文件页数: 25/28页
文件大小: 0K
描述: IC CTRLR PWM BUCK 3PHASE 40-QFN
标准包装: 500
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6308A
0.3
200
100
0.2
50
0.1
20
I L,PP = 0
I L,PP = 0.5 I O
10
100k
200k 500k 1M
SWITCHING FREQUENCY (Hz)
2M
0
0
I L,PP = 0.75 I O
0.2
0.4
0.6
0.8
1.0
FIGURE 23. R FS vs SWITCHING FREQUENCY
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
DUTY CYCLE (V IN/ V O )
FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
0.6
0.3
I L,PP = 0
I L,PP = 0.5 I O
0.4
0.2
I L,PP = 0.25 I O
I L,PP = 0.75 I O
0.2
I L,PP = 0
I L,PP = 0.5 I O
I L,PP = 0.75 I O
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V IN /V O )
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR SINGLE-PHASE CONVERTER
0
0
0.2
0.4
0.6
0.8
1.0
Low ESL, high-frequency ceramic capacitors are needed in
DUTY CYCLE (V IN/ V O )
FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER
For a three-phase design, use Figure 24 to determine the
input-capacitor RMS current requirement set by the duty
cycle, maximum sustained output current (I O ), and the ratio
of the peak-to-peak inductor current (I L,PP ) to I O . Select a
bulk capacitor with a ripple current rating which will minimize
the total number of input capacitors required to support the
RMS current calculated. The voltage rating of the capacitors
should also be at least 1.25 times greater than the maximum
input voltage. Figures 25 and 26 provide the same input
RMS current information for two-phase and single-phase
designs respectively. Use the same approach for selecting
the bulk capacitor type and number.
25
addition to the input bulk capacitors to suppress leading and
falling edge voltage spikes. The spikes result from the high
current slew rate produced by the upper MOSFET turn on
and off. Place them as close as possible to each upper
MOSFET drain to minimize board parasitics and maximize
suppression.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
FN6669.0
September 9, 2008
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