参数资料
型号: ISL6308CRZ
厂商: Intersil
文件页数: 11/28页
文件大小: 0K
描述: IC CTRLR PWM 3PHASE BUCK 40-QFN
标准包装: 500
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6308
V COMP
+
-
+
-
PWM1
TO GATE
CONTROL
LOGIC
each channel in the converter, but may not be active
depending on the status of the PVCC3 and PVCC2 pins, as
FILTER
f(s)
SAWTOOTH SIGNAL
V IN
DS ( ON )
I ER
-
I AVG
÷ N
Σ
I 3
I n
I
r
R
SEN = I L x --------------------------
ISEN
CHANNEL N
UPPER MOSFET
+
I 2
SAMPLE
I L
I 1
NOTE: CHANNEL 2 AND 3 ARE OPTIONAL.
FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
AND
HOLD
-
+
ISEN(n)
R ISEN
-
I L x r DS ( ON )
+
CHANNEL N
Current Sampling
In order to realize proper current balance, the currents in
ISL6308 INTERNAL CIRCUIT
LOWER MOSFET
EXTERNAL CIRCUIT
each channel must be sampled every switching cycle. This
sampling occurs during the forced off-time, following a PWM
transition low. During this time the current sense amplifier
uses the ISEN inputs to reproduce a signal proportional to
the inductor current, I L . This sensed current, I SEN , is simply
a scaled version of the inductor current. The sample window
opens exactly one sixth of the switching period, t SW , after
the PWM transitions low. The sample window then stays
open the rest of the switching cycle until PWM transitions
high again, as illustrated in Figure 4.
The sampled current, at the end of the t SAMPLE , is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used only
FIGURE 5. ISL6308 INTERNAL AND EXTERNAL CURRENT-
SENSING CIRCUITRY FOR CURRENT BALANCE
The ISL6308 senses the channel load current by sampling
the voltage across the lower MOSFET r DS(ON) , as shown in
Figure 5. A ground-referenced operational amplifier, internal
to the ISL6308, is connected to the PHASE node through a
resistor, R ISEN . The voltage across R ISEN is equivalent to
the voltage drop across the r DS(ON) of the lower MOSFET
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, I L . The ISEN current is
sampled and held as described in “Current Sampling” on
page 11. From Figure 5, Equation 3 for I n is derived where I L
is the channel current.
I n = I L ? ----------------------
for channel current balance.
I L
r DS ( ON )
R ISEN
Output Voltage Setting
(EQ. 3)
The ISL6308 uses a digital to analog converter (DAC) to
PWM
SWITCHING PERIOD
I SEN
SAMPLING PERIOD
generate a reference voltage based on the logic signals at the
REF1, REF0 pins. The DAC decodes the 2-bit logic signals
into one of the discrete voltages shown in Table 1. Each REF0
and REF1 pins are pulled up to an internal 1.2V voltage by
weak current sources (40μA current, decreasing to 0 as the
voltage at the REF0, REF1 pins varies from 0 to the internal
1.2V pull-up voltage). External pull-up resistors or active-high
output stages can augment the pull-up current sources, up to
a voltage of 5V. The DAC pin must be connected to REF pin
through a 1k Ω to 5k Ω resistor and a filter capacitor (0.022μF)
OLD SAMPLE
NEW SAMPLE
is connected between REF and GND.
CURRENT
TIME
CURRENT
The ISL6308 accommodates the use of external voltage
reference connected to REF pin if a different output voltage
FIGURE 4. SAMPLE AND HOLD TIMING
The ISL6308 supports MOSFET r DS(ON) current sensing to
sample each channel’s current for channel current balance.
The internal circuitry, shown in Figure 5 represents Channel
N of an N-channel converter. This circuitry is repeated for
11
is required. The DAC voltage must be set at least as high as
the external reference. The error amp internal non-inverting
input is the lower of REF or (DAC +300mV).
A third method for setting the output voltage is to use a
resistor divider (R P1 , R S1 ) from the output terminal (V OUT )
FN9208.4
September 30, 2008
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