参数资料
型号: ISL6308CRZ
厂商: Intersil
文件页数: 15/28页
文件大小: 0K
描述: IC CTRLR PWM 3PHASE BUCK 40-QFN
标准包装: 500
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6308
1.6
ISL6308 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
1.4
VCC
1.2
1.0
0.8
POR
PVCC1
+ 12 V
0.6
0.4
Q GATE = 100nC
CIRCUIT
ENABLE
COMPARATOR
+
10.7k Ω
ENLL
0.2
20nC
50nC
-
1.40k Ω
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.66V
Δ V BOOT_CAP (V)
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6308 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the
ENLL, VCC, PVCC and the REF0 and REF1 pins. When the
conditions are met, the controller begins soft-start. Once the
output voltage is within the proper window of operation, the
controller asserts PGOOD.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6308 is
released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6308 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6308 will not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical
Specifications” on page 5).
15
SOFT-START
AND
FAULT LOGIC
FIGURE 11. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (ENLL) FUNCTION
2. The voltage on ENLL must be above 0.66V. The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6308 in shutdown until the voltage at ENLL
rises above 0.66V. The enable comparator has 100mV of
hysteresis to prevent bounce.
3. The driver bias voltage applied at the PVCC pins must
reach the internal power-on reset (POR) rising threshold.
In order for the ISL6308 to begin operation, PVCC1 is the
only pin that is required to have a voltage applied that
exceeds POR. However, for 2 or 3-phase operation
PVCC2 and PVCC3 must also exceed the POR
threshold. Hysteresis between the rising and falling
thresholds assure that once enabled, the ISL6308 will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see “Electrical Specifications” on page 5).
When each of these conditions is true, the controller
immediately begins the soft-start sequence.
Soft-Start
During soft-start, the DAC voltage ramps linearly from zero to
the programmed level. The PWM signals remain in the high-
impedance state until the controller detects that the ramping
DAC level has reached the output-voltage level. This protects
the system against the large, negative inductor currents that
would otherwise occur when starting with a pre-existing
charge on the output as the controller attempted to regulate to
zero volts at the beginning of the soft-start cycle. The Output
soft-start time, t SS , begins with a delay period equal to 64
switching cycles after the ENLL has exceeded its POR level,
FN9208.4
September 30, 2008
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